Lines Matching defs:res_pool

230 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
349 for (i = 0; i < dc->res_pool->pipe_count; i++) {
380 for (i = 0; i < dc->res_pool->pipe_count; i++) {
401 for (i = 0; i < dc->res_pool->pipe_count; i++) {
440 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
476 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
522 struct mpc *mpc = dc->res_pool->mpc;
564 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
603 for (i = 0; i < dc->res_pool->pipe_count; i++) {
618 for (i = 0; i < dc->res_pool->pipe_count; i++) {
642 for (i = 0; i < dc->res_pool->pipe_count; i++) {
702 for (i = 0; i < dc->res_pool->pipe_count; i++) {
749 struct abm **abms = dc->res_pool->multiple_abms;
752 struct resource_pool *res_pool = dc->res_pool;
762 if (res_pool->dccg->funcs->dccg_init)
763 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
782 res_pool->ref_clocks.xtalin_clock_inKhz =
785 if (res_pool->dccg && res_pool->hubbub) {
786 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
788 &res_pool->ref_clocks.dccg_ref_clock_inKhz);
790 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
791 res_pool->ref_clocks.dccg_ref_clock_inKhz,
792 &res_pool->ref_clocks.dchub_ref_clock_inKhz);
795 res_pool->ref_clocks.dccg_ref_clock_inKhz =
796 res_pool->ref_clocks.xtalin_clock_inKhz;
797 res_pool->ref_clocks.dchub_ref_clock_inKhz =
798 res_pool->ref_clocks.xtalin_clock_inKhz;
847 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
848 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
849 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
902 for (i = 0; i < res_pool->audio_count; i++) {
903 struct audio *audio = res_pool->audios[i];
917 for (i = 0; i < dc->res_pool->pipe_count; i++) {
934 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
935 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
943 if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
944 dc->res_pool->hubbub->funcs->force_pstate_change_control(
945 dc->res_pool->hubbub, false, false);
947 if (dc->res_pool->hubbub->funcs->init_crb)
948 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
950 if (dc->res_pool->hubbub->funcs->set_request_limit && dc->config.sdpif_request_limit_words_per_umc > 0)
951 dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, dc->ctx->dc_bios->vram_info.num_chans, dc->config.sdpif_request_limit_words_per_umc);
976 struct dccg *dccg = dc->res_pool->dccg;
1110 struct dccg *dccg = dc->res_pool->dccg;
1187 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1201 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg);
1203 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1307 struct dmcu *dmcu = dc->res_pool->dmcu;
1342 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1427 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1428 struct display_stream_compressor *dsc = dc->res_pool->dscs[i];
1448 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1482 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1500 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1563 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) {
1568 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1569 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1570 opp = dc->res_pool->opps[i];
1578 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) {
1582 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1583 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src1) {
1584 bottom_opp = dc->res_pool->opps[i];
1642 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
1644 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1645 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1646 opp = dc->res_pool->opps[i];
1674 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1755 for (i = 0; i < dc->res_pool->pipe_count; i++) {