hwss/dcn31/dcn31_hwseq.c

57 	hws->ctx
59 	hws->regs->reg
66 	hws->shifts->field_name, hws->masks->field_name
70 	struct dce_hwseq *hws = dc->hwseq;
110 	struct dce_hwseq *hws = dc->hwseq;
121 		hws->funcs.bios_golden_init(dc);
122 		if (hws->funcs.disable_vga)
123 			hws->funcs.disable_vga(dc->hwseq);
179 	if (hws->funcs.enable_power_gating_plane)
180 		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
211 		hws->funcs.init_pipes(dc, dc->current_state);
244 	if (hws->funcs.setup_hpo_hw_control)
245 		hws->funcs.setup_hpo_hw_control(hws, false);
280 		struct dce_hwseq *hws,
288 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
291 	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
292 		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
294 		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
295 			hws->ctx->dc->res_pool->dccg, dsc_inst);
334 	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
335 		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
336 			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
337 				hws->ctx->dc->res_pool->dccg, dsc_inst);
344 	struct dce_hwseq *hws,
350 	if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
364 	if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
441 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
446 	if (hws->ctx->dc->debug.disable_hubp_power_gate)
480 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
572 	struct dce_hwseq *hws = dc->hwseq;
602 			if (hws->funcs.enable_stream_gating)
603 				hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
613 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
615 	if (hws->ctx->dc->debug.hpo_optimization)