Lines Matching defs:dc
88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
97 void dcn10_lock_all_pipes(struct dc *dc,
106 for (i = 0; i < dc->res_pool->pipe_count; i++) {
107 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
123 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
125 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
129 static void log_mpc_crc(struct dc *dc,
132 struct dc_context *dc_ctx = dc->ctx;
133 struct dce_hwseq *hws = dc->hwseq;
143 static void dcn10_log_hubbub_state(struct dc *dc,
146 struct dc_context *dc_ctx = dc->ctx;
151 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
172 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
174 struct dc_context *dc_ctx = dc->ctx;
175 struct resource_pool *pool = dc->res_pool;
286 static void dcn10_log_color_state(struct dc *dc,
289 struct dc_context *dc_ctx = dc->ctx;
290 struct resource_pool *pool = dc->res_pool;
354 dc->caps.color.dpp.input_lut_shared,
355 dc->caps.color.dpp.icsc,
356 dc->caps.color.dpp.dgam_ram,
357 dc->caps.color.dpp.dgam_rom_caps.srgb,
358 dc->caps.color.dpp.dgam_rom_caps.bt2020,
359 dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
360 dc->caps.color.dpp.dgam_rom_caps.pq,
361 dc->caps.color.dpp.dgam_rom_caps.hlg,
362 dc->caps.color.dpp.post_csc,
363 dc->caps.color.dpp.gamma_corr,
364 dc->caps.color.dpp.dgam_rom_for_yuv,
365 dc->caps.color.dpp.hw_3d_lut,
366 dc->caps.color.dpp.ogam_ram,
367 dc->caps.color.dpp.ocsc);
382 dc->caps.color.mpc.gamut_remap,
383 dc->caps.color.mpc.num_3dluts,
384 dc->caps.color.mpc.ogam_ram,
385 dc->caps.color.mpc.ocsc);
388 void dcn10_log_hw_state(struct dc *dc,
391 struct dc_context *dc_ctx = dc->ctx;
392 struct resource_pool *pool = dc->res_pool;
397 dcn10_log_hubbub_state(dc, log_ctx);
399 dcn10_log_hubp_states(dc, log_ctx);
401 if (dc->hwss.log_color_state)
402 dc->hwss.log_color_state(dc, log_ctx);
404 dcn10_log_color_state(dc, log_ctx);
498 for (i = 0; i < dc->link_count; i++) {
499 struct link_encoder *lenc = dc->links[i]->link_enc;
518 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
519 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
520 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
521 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
522 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
523 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
524 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
526 log_mpc_crc(dc, log_ctx);
590 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
679 if (hws->ctx->dc->debug.disable_dpp_power_gate)
740 if (hws->ctx->dc->debug.disable_hubp_power_gate)
810 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
812 struct dce_hwseq *hws = dc->hwseq;
813 struct hubp *hubp = dc->res_pool->hubps[0];
830 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
832 struct dce_hwseq *hws = dc->hwseq;
833 struct hubp *hubp = dc->res_pool->hubps[0];
836 if (dc->debug.disable_stutter)
842 for (i = 0; i < dc->res_pool->pipe_count; i++) {
843 if (!dc->res_pool->hubps[i]->power_gated)
860 void dcn10_bios_golden_init(struct dc *dc)
862 struct dce_hwseq *hws = dc->hwseq;
863 struct dc_bios *bp = dc->ctx->dc_bios;
867 if (hws->funcs.s0i3_golden_init_wa && hws->funcs.s0i3_golden_init_wa(dc))
870 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
872 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
886 for (i = 0; i < dc->res_pool->pipe_count; i++) {
892 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
894 dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
895 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
896 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
901 struct dc *dc,
908 if (!dc->hwseq->wa.false_optc_underflow)
913 for (i = 0; i < dc->res_pool->pipe_count; i++) {
914 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
919 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
958 struct dc *dc)
981 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1018 color_space_to_black_color(dc, color_space, &black_color);
1037 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
1058 struct dc *dc,
1064 DC_LOGGER_INIT(dc->ctx->logger);
1078 dc->link_srv->set_dpms_off(pipe_ctx);
1080 dc->hwss.disable_audio_stream(pipe_ctx);
1087 if (dc->caps.dynamic_audio == true) {
1090 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
1103 dc->hwss.set_abm_immediate_disable(pipe_ctx);
1115 for (i = 0; i < dc->res_pool->pipe_count; i++)
1116 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
1119 if (i == dc->res_pool->pipe_count)
1127 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
1133 if (!dc->debug.recovery_enabled)
1136 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1138 &dc->current_state->res_ctx.pipe_ctx[i];
1161 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1163 &dc->current_state->res_ctx.pipe_ctx[i];
1172 hubbub1_soft_reset(dc->res_pool->hubbub, true);
1174 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1176 &dc->current_state->res_ctx.pipe_ctx[i];
1184 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1186 &dc->current_state->res_ctx.pipe_ctx[i];
1195 hubbub1_soft_reset(dc->res_pool->hubbub, false);
1196 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1198 &dc->current_state->res_ctx.pipe_ctx[i];
1210 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
1212 struct hubbub *hubbub = dc->res_pool->hubbub;
1222 dcn10_log_hw_state(dc, NULL);
1226 if (dcn10_hw_wa_force_recovery(dc)) {
1235 void dcn10_plane_atomic_disconnect(struct dc *dc,
1239 struct dce_hwseq *hws = dc->hwseq;
1242 struct mpc *mpc = dc->res_pool->mpc;
1260 dc->optimized_required = true;
1265 if (dc->debug.sanity_checks)
1266 hws->funcs.verify_allow_pstate_change_high(dc);
1272 * @dc: dc struct reference. used for grab hwseq.
1282 void dcn10_plane_atomic_power_down(struct dc *dc,
1286 struct dce_hwseq *hws = dc->hwseq;
1287 DC_LOGGER_INIT(dc->ctx->logger);
1314 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
1316 struct dce_hwseq *hws = dc->hwseq;
1321 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
1333 dc->optimized_required = false; /* We're powering off, no need to optimize */
1335 hws->funcs.plane_atomic_power_down(dc,
1347 void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)
1349 struct dce_hwseq *hws = dc->hwseq;
1350 DC_LOGGER_INIT(dc->ctx->logger);
1355 hws->funcs.plane_atomic_disable(dc, pipe_ctx);
1357 apply_DEGVIDCN10_253_wa(dc);
1363 void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
1366 struct dce_hwseq *hws = dc->hwseq;
1367 struct hubbub *hubbub = dc->res_pool->hubbub;
1378 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1379 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1394 hws->funcs.init_blank(dc, tg);
1405 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1407 struct hubp *hubp = dc->res_pool->hubps[i];
1420 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1427 dc->res_pool->mpc->funcs->mpc_init_single_inst(
1428 dc->res_pool->mpc, i);
1431 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1432 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1433 struct hubp *hubp = dc->res_pool->hubps[i];
1434 struct dpp *dpp = dc->res_pool->dpps[i];
1456 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1470 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1471 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1472 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1473 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1475 hws->funcs.plane_atomic_disconnect(dc, context, pipe_ctx);
1480 dc->hwss.disable_plane(dc, context, pipe_ctx);
1494 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1496 if (dc->res_pool->opps[i]->mpc_tree_params.opp_list) {
1497 if (dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot) {
1498 int bot_id = dc->res_pool->opps[i]->mpc_tree_params.opp_list->mpcc_bot->mpcc_id;
1501 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1519 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1521 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1536 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1539 dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s);
1545 hws->funcs.dsc_pg_control(hws, dc->res_pool->dscs[i]->inst, false);
1550 void dcn10_init_hw(struct dc *dc)
1553 struct abm *abm = dc->res_pool->abm;
1554 struct dmcu *dmcu = dc->res_pool->dmcu;
1555 struct dce_hwseq *hws = dc->hwseq;
1556 struct dc_bios *dcb = dc->ctx->dc_bios;
1557 struct resource_pool *res_pool = dc->res_pool;
1562 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
1563 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
1566 if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
1567 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;
1568 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;
1572 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
1573 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
1576 hws->funcs.disable_vga(dc->hwseq);
1578 if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))
1579 hws->funcs.bios_golden_init(dc);
1582 if (dc->ctx->dc_bios->fw_info_valid) {
1584 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
1589 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
1605 for (i = 0; i < dc->link_count; i++) {
1610 struct dc_link *link = dc->links[i];
1626 dc->link_srv->blank_all_dp_displays(dc);
1629 hws->funcs.enable_power_gating_plane(dc->hwseq, true);
1637 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
1639 hws->funcs.init_pipes(dc, dc->current_state);
1640 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
1641 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
1642 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
1654 for (i = 0; i < dc->link_count; i++) {
1655 struct dc_link *link = dc->links[i];
1677 if (!dc->debug.disable_clock_gate) {
1686 if (dc->clk_mgr->funcs->notify_wm_ranges)
1687 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
1695 void dcn10_power_down_on_boot(struct dc *dc)
1702 dc_get_edp_links(dc, edp_links, &edp_num);
1708 dc->hwseq->funcs.edp_backlight_control &&
1709 dc->hwss.power_down &&
1710 dc->hwss.edp_power_control) {
1711 dc->hwseq->funcs.edp_backlight_control(edp_link, false);
1712 dc->hwss.power_down(dc);
1713 dc->hwss.edp_power_control(edp_link, false);
1715 for (i = 0; i < dc->link_count; i++) {
1716 struct dc_link *link = dc->links[i];
1720 dc->hwss.power_down) {
1721 dc->hwss.power_down(dc);
1733 if (dc->clk_mgr->funcs->set_low_power_state)
1734 dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);
1738 struct dc *dc,
1742 struct dce_hwseq *hws = dc->hwseq;
1745 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1747 &dc->current_state->res_ctx.pipe_ctx[i];
1760 dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1762 hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
1797 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1822 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1834 if (!dpp_base->ctx->dc->debug.always_use_regamma
1902 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
1922 else if (cm_helper_translate_curve_to_hw_format(dc->ctx,
1941 struct dc *dc,
1945 struct dce_hwseq *hws = dc->hwseq;
1953 if (dc->debug.sanity_checks)
1954 hws->funcs.verify_allow_pstate_change_high(dc);
1961 if (dc->debug.sanity_checks)
1962 hws->funcs.verify_allow_pstate_change_high(dc);
1978 * @dc: Current DC state
1983 static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx)
1991 if (!dc->hwss.calc_vupdate_position || !dc->hwss.get_position)
1997 dc->hwss.calc_vupdate_position(dc, pipe_ctx, &vupdate_start,
2000 dc->hwss.get_position(&pipe_ctx, 1, &position);
2035 void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
2043 delay_cursor_until_vupdate(dc, pipe);
2052 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2057 dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc,
2180 static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
2183 struct dc_context *dc_ctx = dc->ctx;
2194 dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;
2202 if (dc->config.vblank_alignment_dto_params &&
2203 dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {
2205 (dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF;
2207 (dc->config.vblank_alignment_dto_params >> 48) & 0x7FFF;
2209 dc->config.vblank_alignment_dto_params & 0xFFFFFFFF;
2215 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
2216 dc->res_pool->dp_clock_source,
2250 dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk(
2251 dc->res_pool->dp_clock_source,
2254 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
2255 dc->res_pool->dp_clock_source,
2271 struct dc *dc,
2276 struct dc_context *dc_ctx = dc->ctx;
2306 master = dcn10_align_pixel_clocks(dc, group_size, grouped_pipes);
2336 struct dc *dc,
2342 struct dc_context *dc_ctx = dc->ctx;
2419 struct dc *dc,
2423 struct dc_context *dc_ctx = dc->ctx;
2528 struct dc *dc,
2532 struct dce_hwseq *hws = dc->hwseq;
2534 if (dc->debug.sanity_checks) {
2535 hws->funcs.verify_allow_pstate_change_high(dc);
2538 undo_DEGVIDCN10_253_wa(dc);
2540 power_on_plane_resources(dc->hwseq,
2551 if (dc->config.gpu_vm_support)
2554 if (dc->debug.sanity_checks) {
2555 hws->funcs.verify_allow_pstate_change_high(dc);
2620 void dcn10_program_output_csc(struct dc *dc,
2670 void dcn10_update_visual_confirm_color(struct dc *dc,
2674 struct mpc *mpc = dc->res_pool->mpc;
2682 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2689 struct mpc *mpc = dc->res_pool->mpc;
2731 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
2741 if (dc->debug.sanity_checks)
2743 dc->res_pool->mpc, mpcc_id);
2746 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2753 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id);
2773 struct dc *dc,
2777 struct dce_hwseq *hws = dc->hwseq;
2793 * dispclk, dppclk are from dc->clk_mgr->clks.dispclk_khz.
2817 dc->clk_mgr->clks.dispclk_khz)
2822 dc->clk_mgr->clks.dispclk_khz / 2;
2829 if (dc->res_pool->dccg)
2830 dc->res_pool->dccg->funcs->update_dpp_dto(
2831 dc->res_pool->dccg,
2835 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2836 dc->clk_mgr->clks.dispclk_khz / 2 :
2837 dc->clk_mgr->clks.dispclk_khz;
2868 hws->funcs.update_mpcc(dc, pipe_ctx);
2888 dc->hwss.set_cursor_position(pipe_ctx);
2889 dc->hwss.set_cursor_attribute(pipe_ctx);
2891 if (dc->hwss.set_cursor_sdr_white_level)
2892 dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
2897 dc->hwss.program_gamut_remap(pipe_ctx);
2899 dc->hwss.program_output_csc(dc,
2928 hws->funcs.update_plane_addr(dc, pipe_ctx);
2935 struct dc *dc,
2946 color_space_to_black_color(dc, color_space, &black_color);
2966 dc->hwss.set_pipe(pipe_ctx);
2970 dc->hwss.set_abm_immediate_disable(pipe_ctx);
2997 struct dc *dc,
3001 struct dce_hwseq *hws = dc->hwseq;
3017 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
3019 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
3023 dcn10_enable_plane(dc, pipe_ctx, context);
3025 dcn10_update_dchubp_dpp(dc, pipe_ctx, context);
3032 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
3041 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
3044 void dcn10_wait_for_pending_cleared(struct dc *dc,
3051 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3077 struct dc *dc,
3082 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3091 false_optc_underflow_wa(dc, pipe_ctx->stream, tg);
3095 for (i = 0; i < dc->res_pool->pipe_count; i++)
3097 dc->hwss.disable_plane(dc, dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
3099 for (i = 0; i < dc->res_pool->pipe_count; i++)
3101 dc->hwss.optimize_bandwidth(dc, context);
3105 if (dc->hwseq->wa.DEGVIDCN10_254)
3106 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
3109 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
3119 hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
3126 struct dc *dc,
3129 struct dce_hwseq *hws = dc->hwseq;
3130 struct hubbub *hubbub = dc->res_pool->hubbub;
3133 if (dc->debug.sanity_checks)
3134 hws->funcs.verify_allow_pstate_change_high(dc);
3139 dc->clk_mgr->funcs->update_clocks(
3140 dc->clk_mgr,
3144 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub,
3146 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
3148 dcn10_stereo_hw_frame_pack_wa(dc, context);
3150 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
3153 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
3156 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
3159 if (dc->debug.sanity_checks)
3160 hws->funcs.verify_allow_pstate_change_high(dc);
3164 struct dc *dc,
3167 struct dce_hwseq *hws = dc->hwseq;
3168 struct hubbub *hubbub = dc->res_pool->hubbub;
3171 if (dc->debug.sanity_checks)
3172 hws->funcs.verify_allow_pstate_change_high(dc);
3177 dc->clk_mgr->funcs->update_clocks(
3178 dc->clk_mgr,
3184 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
3187 dcn10_stereo_hw_frame_pack_wa(dc, context);
3189 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
3192 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
3195 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
3198 if (dc->debug.sanity_checks)
3199 hws->funcs.verify_allow_pstate_change_high(dc);
3307 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
3315 if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
3316 dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
3318 dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
3347 struct dc *dc,
3351 struct dce_hwseq *hws = dc->hwseq;
3354 if (dc->debug.sanity_checks) {
3355 hws->funcs.verify_allow_pstate_change_high(dc);
3373 if (dc->debug.sanity_checks) {
3374 hws->funcs.verify_allow_pstate_change_high(dc);
3380 struct dc *dc,
3393 struct dc *dc = pipe_ctx->stream->ctx->dc;
3412 if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) {
3413 struct dce_hwseq *hwseq = dc->hwseq;
3414 struct timing_generator *tg = dc->res_pool->timing_generators[0];
3418 struct hubbub *hubbub = dc->res_pool->hubbub;
3420 hubbub->funcs->allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);
3428 struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
3488 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
3551 * cursor on both streams while expecting dc to clip it.
3802 struct dc *dc,
3808 int vupdate_pos = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3818 struct dc *dc,
3832 vline_pos += dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3847 struct dc *dc,
3854 dcn10_cal_vline_position(dc, pipe_ctx, &start_line, &end_line);
3859 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
3862 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
3879 struct dce_hwseq *hws = link->dc->hwseq;
3908 enum dc_status dcn10_set_clock(struct dc *dc,
3913 struct dc_state *context = dc->current_state;
3917 if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_clock)
3920 dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
3940 if (dc->clk_mgr->funcs->update_clocks)
3941 dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
3947 void dcn10_get_clock(struct dc *dc,
3951 struct dc_state *context = dc->current_state;
3953 if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
3954 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
3958 void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits)
3960 struct resource_pool *pool = dc->res_pool;