Lines Matching refs:type
263 #define DSC_FIELD_LIST_DCN20(type)\
264 type DSC_CLOCK_EN; \
265 type DSC_DISPCLK_R_GATE_DIS; \
266 type DSC_DSCCLK_R_GATE_DIS; \
267 type DSC_DBG_EN; \
268 type DSC_TEST_CLOCK_MUX_SEL; \
269 type ICH_RESET_AT_END_OF_LINE; \
270 type NUMBER_OF_SLICES_PER_LINE; \
271 type ALTERNATE_ICH_ENCODING_EN; \
272 type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
273 type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
274 /*type DSCC_DISABLE_ICH;*/ \
275 type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
276 type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
277 type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \
278 type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED; \
279 type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED; \
280 type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED; \
281 type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED; \
282 type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED; \
283 type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED; \
284 type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED; \
285 type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED; \
286 type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED; \
287 type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED; \
288 type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN; \
289 type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN; \
290 type DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN; \
291 type DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN; \
292 type DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN; \
293 type DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN; \
294 type DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN; \
295 type DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN; \
296 type DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN; \
297 type DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN; \
298 type DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN; \
299 type DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN; \
300 type DSC_VERSION_MINOR; \
301 type DSC_VERSION_MAJOR; \
302 type PPS_IDENTIFIER; \
303 type LINEBUF_DEPTH; \
304 type DSCC_PPS_CONFIG0__BITS_PER_COMPONENT; \
305 type BITS_PER_PIXEL; \
306 type VBR_ENABLE; \
307 type SIMPLE_422; \
308 type CONVERT_RGB; \
309 type BLOCK_PRED_ENABLE; \
310 type NATIVE_422; \
311 type NATIVE_420; \
312 type CHUNK_SIZE; \
313 type PIC_WIDTH; \
314 type PIC_HEIGHT; \
315 type SLICE_WIDTH; \
316 type SLICE_HEIGHT; \
317 type INITIAL_XMIT_DELAY; \
318 type INITIAL_DEC_DELAY; \
319 type INITIAL_SCALE_VALUE; \
320 type SCALE_INCREMENT_INTERVAL; \
321 type SCALE_DECREMENT_INTERVAL; \
322 type FIRST_LINE_BPG_OFFSET; \
323 type SECOND_LINE_BPG_OFFSET; \
324 type NFL_BPG_OFFSET; \
325 type SLICE_BPG_OFFSET; \
326 type NSL_BPG_OFFSET; \
327 type SECOND_LINE_OFFSET_ADJ; \
328 type INITIAL_OFFSET; \
329 type FINAL_OFFSET; \
330 type FLATNESS_MIN_QP; \
331 type FLATNESS_MAX_QP; \
332 type RC_MODEL_SIZE; \
333 type RC_EDGE_FACTOR; \
334 type RC_QUANT_INCR_LIMIT0; \
335 type RC_QUANT_INCR_LIMIT1; \
336 type RC_TGT_OFFSET_LO; \
337 type RC_TGT_OFFSET_HI; \
338 type RC_BUF_THRESH0; \
339 type RC_BUF_THRESH1; \
340 type RC_BUF_THRESH2; \
341 type RC_BUF_THRESH3; \
342 type RC_BUF_THRESH4; \
343 type RC_BUF_THRESH5; \
344 type RC_BUF_THRESH6; \
345 type RC_BUF_THRESH7; \
346 type RC_BUF_THRESH8; \
347 type RC_BUF_THRESH9; \
348 type RC_BUF_THRESH10; \
349 type RC_BUF_THRESH11; \
350 type RC_BUF_THRESH12; \
351 type RC_BUF_THRESH13; \
352 type RANGE_MIN_QP0; \
353 type RANGE_MAX_QP0; \
354 type RANGE_BPG_OFFSET0; \
355 type RANGE_MIN_QP1; \
356 type RANGE_MAX_QP1; \
357 type RANGE_BPG_OFFSET1; \
358 type RANGE_MIN_QP2; \
359 type RANGE_MAX_QP2; \
360 type RANGE_BPG_OFFSET2; \
361 type RANGE_MIN_QP3; \
362 type RANGE_MAX_QP3; \
363 type RANGE_BPG_OFFSET3; \
364 type RANGE_MIN_QP4; \
365 type RANGE_MAX_QP4; \
366 type RANGE_BPG_OFFSET4; \
367 type RANGE_MIN_QP5; \
368 type RANGE_MAX_QP5; \
369 type RANGE_BPG_OFFSET5; \
370 type RANGE_MIN_QP6; \
371 type RANGE_MAX_QP6; \
372 type RANGE_BPG_OFFSET6; \
373 type RANGE_MIN_QP7; \
374 type RANGE_MAX_QP7; \
375 type RANGE_BPG_OFFSET7; \
376 type RANGE_MIN_QP8; \
377 type RANGE_MAX_QP8; \
378 type RANGE_BPG_OFFSET8; \
379 type RANGE_MIN_QP9; \
380 type RANGE_MAX_QP9; \
381 type RANGE_BPG_OFFSET9; \
382 type RANGE_MIN_QP10; \
383 type RANGE_MAX_QP10; \
384 type RANGE_BPG_OFFSET10; \
385 type RANGE_MIN_QP11; \
386 type RANGE_MAX_QP11; \
387 type RANGE_BPG_OFFSET11; \
388 type RANGE_MIN_QP12; \
389 type RANGE_MAX_QP12; \
390 type RANGE_BPG_OFFSET12; \
391 type RANGE_MIN_QP13; \
392 type RANGE_MAX_QP13; \
393 type RANGE_BPG_OFFSET13; \
394 type RANGE_MIN_QP14; \
395 type RANGE_MAX_QP14; \
396 type RANGE_BPG_OFFSET14; \
397 type DSCC_DEFAULT_MEM_LOW_POWER_STATE; \
398 type DSCC_MEM_PWR_FORCE; \
399 type DSCC_MEM_PWR_DIS; \
400 type DSCC_MEM_PWR_STATE; \
401 type DSCC_NATIVE_422_MEM_PWR_FORCE; \
402 type DSCC_NATIVE_422_MEM_PWR_DIS; \
403 type DSCC_NATIVE_422_MEM_PWR_STATE; \
404 type DSCC_R_Y_SQUARED_ERROR_LOWER; \
405 type DSCC_R_Y_SQUARED_ERROR_UPPER; \
406 type DSCC_G_CB_SQUARED_ERROR_LOWER; \
407 type DSCC_G_CB_SQUARED_ERROR_UPPER; \
408 type DSCC_B_CR_SQUARED_ERROR_LOWER; \
409 type DSCC_B_CR_SQUARED_ERROR_UPPER; \
410 type DSCC_R_Y_MAX_ABS_ERROR; \
411 type DSCC_G_CB_MAX_ABS_ERROR; \
412 type DSCC_B_CR_MAX_ABS_ERROR; \
413 type DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL; \
414 type DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL; \
415 type DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL; \
416 type DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL; \
417 type DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL; \
418 type DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL; \
419 type DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL; \
420 type DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL; \
421 type DSCC_UPDATE_PENDING_STATUS; \
422 type DSCC_UPDATE_TAKEN_STATUS; \
423 type DSCC_UPDATE_TAKEN_ACK; \
424 type DSCC_RATE_BUFFER0_FULLNESS_LEVEL; \
425 type DSCC_RATE_BUFFER1_FULLNESS_LEVEL; \
426 type DSCC_RATE_BUFFER2_FULLNESS_LEVEL; \
427 type DSCC_RATE_BUFFER3_FULLNESS_LEVEL; \
428 type DSCC_RATE_CONTROL_BUFFER0_FULLNESS_LEVEL; \
429 type DSCC_RATE_CONTROL_BUFFER1_FULLNESS_LEVEL; \
430 type DSCC_RATE_CONTROL_BUFFER2_FULLNESS_LEVEL; \
431 type DSCC_RATE_CONTROL_BUFFER3_FULLNESS_LEVEL; \
432 type DSCC_RATE_BUFFER0_INITIAL_XMIT_DELAY_REACHED; \
433 type DSCC_RATE_BUFFER1_INITIAL_XMIT_DELAY_REACHED; \
434 type DSCC_RATE_BUFFER2_INITIAL_XMIT_DELAY_REACHED; \
435 type DSCC_RATE_BUFFER3_INITIAL_XMIT_DELAY_REACHED; \
436 type INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN; \
437 type INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN; \
438 type INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS; \
439 type INPUT_PIXEL_FORMAT; \
440 type DSCCIF_CONFIG0__BITS_PER_COMPONENT; \
441 type DOUBLE_BUFFER_REG_UPDATE_PENDING; \
442 type DSCCIF_UPDATE_PENDING_STATUS; \
443 type DSCCIF_UPDATE_TAKEN_STATUS; \
444 type DSCCIF_UPDATE_TAKEN_ACK; \
445 type DSCRM_DSC_FORWARD_EN; \
446 type DSCRM_DSC_OPP_PIPE_SOURCE