dc/dml2/dml2_wrapper.c

73 		if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
74 			dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
84 			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];
85 			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;
86 			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];
87 			dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true;
97 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
99 	s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx;
230 	struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch;
231 	struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch;
236 	build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);
261 	for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {
262 		s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us;
266 		for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) {
267 			dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us;
274 			dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);
278 			dml2_extract_watermark_set(&dml2->v20.g6_temp_read_watermark_set, &dml2->v20.dml_core_ctx);
279 			dml2->v20.g6_temp_read_watermark_set.cstate_pstate.fclk_pstate_change_ns = dml2->v20.g6_temp_read_watermark_set.cstate_pstate.pstate_change_ns;
283 			while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram_speed_mts)
290 	for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) {
291 		dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latencies[i];
337 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
341 	build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);
378 		s->cur_policy = dml2->v20.dml_core_ctx.policy;
379 		s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx;
381 		s->optimize_configuration_params.ip_params = &dml2->v20.dml_core_ctx.ip;
389 			dml2->v20.dml_core_ctx.policy = s->new_policy;
403 				dml2->v20.dml_core_ctx.policy = s->cur_policy;
438 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
467 			result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true);
540 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
561 		result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true);
569 	struct dml2_wrapper_scratch *s = &dml2->v20.scratch;
579 	memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));
580 	memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));
581 	memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st));
582 	memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st));
617 		out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000;
620 			(lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) {
621 			lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1;
622 			out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000;
625 		out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000;
626 		out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000;
627 		out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts;
628 		out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000;
629 		out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000;
630 		out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000;
639 		dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx);
640 		dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx);
641 		memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c));
642 		dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx);
643 		dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx);
645 		context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod;
668 	memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch));
669 	memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st));
670 	memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st));
671 	memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st));
673 	build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy);
675 	map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config);
678 		&dml2->v20.scratch.cur_display_config,
679 		&dml2->v20.scratch.mode_support_info);
682 		result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info);
724 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn35;
727 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;
730 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;
733 		(*dml2)->v20.dml_core_ctx.project = dml_project_dcn321;
736 		(*dml2)->v20.dml_core_ctx.project = dml_project_default;
740 	initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);
742 	initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);
744 	initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);
771 	*fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0];
772 	*dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0];