Lines Matching refs:out
33 void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
41 out->vblank_nom_default_us = 600;
42 out->rob_buffer_size_kbytes = 128;
43 out->config_return_buffer_size_in_kbytes = 1280;
44 out->config_return_buffer_segment_size_in_kbytes = 64;
45 out->compressed_buffer_segment_size_in_kbytes = 64;
46 out->meta_fifo_size_in_kentries = 22;
47 out->zero_size_buffer_entries = 512;
48 out->dpte_buffer_size_in_pte_reqs_luma = 68;
49 out->dpte_buffer_size_in_pte_reqs_chroma = 36;
50 out->dcc_meta_buffer_size_bytes = 6272;
51 out->gpuvm_max_page_table_levels = 4;
52 out->hostvm_max_page_table_levels = 0;
53 out->pixel_chunk_size_kbytes = 8;
54 //out->alpha_pixel_chunk_size_kbytes;
55 out->min_pixel_chunk_size_bytes = 1024;
56 out->meta_chunk_size_kbytes = 2;
57 out->min_meta_chunk_size_bytes = 256;
58 out->writeback_chunk_size_kbytes = 8;
59 out->line_buffer_size_bits = 1171920;
60 out->max_line_buffer_lines = 32;
61 out->writeback_interface_buffer_size_kbytes = 90;
63 out->max_num_dpp = dml2->config.dcn_pipe_count;
64 out->max_num_otg = dml2->config.dcn_pipe_count;
65 out->max_num_wb = 1;
66 out->max_dchub_pscl_bw_pix_per_clk = 4;
67 out->max_pscl_lb_bw_pix_per_clk = 2;
68 out->max_lb_vscl_bw_pix_per_clk = 4;
69 out->max_vscl_hscl_bw_pix_per_clk = 4;
70 out->max_hscl_ratio = 6;
71 out->max_vscl_ratio = 6;
72 out->max_hscl_taps = 8;
73 out->max_vscl_taps = 8;
74 out->dispclk_ramp_margin_percent = 1;
75 out->dppclk_delay_subtotal = 47;
76 out->dppclk_delay_scl = 50;
77 out->dppclk_delay_scl_lb_only = 16;
78 out->dppclk_delay_cnvc_formatter = 28;
79 out->dppclk_delay_cnvc_cursor = 6;
80 out->cursor_buffer_size = 16;
81 out->cursor_chunk_size = 2;
82 out->dispclk_delay_subtotal = 125;
83 out->max_inter_dcn_tile_repeaters = 8;
84 out->writeback_max_hscl_ratio = 1;
85 out->writeback_max_vscl_ratio = 1;
86 out->writeback_min_hscl_ratio = 1;
87 out->writeback_min_vscl_ratio = 1;
88 out->writeback_max_hscl_taps = 1;
89 out->writeback_max_vscl_taps = 1;
90 out->writeback_line_buffer_buffer_size = 0;
91 out->num_dsc = 4;
92 out->maximum_dsc_bits_per_component = 12;
93 out->maximum_pixels_per_line_per_dsc_unit = 6016;
94 out->dsc422_native_support = true;
95 out->dcc_supported = true;
96 out->ptoi_supported = false;
98 out->gpuvm_enable = false;
99 out->hostvm_enable = false;
100 out->cursor_64bpp_support = false;
101 out->dynamic_metadata_vm_enabled = false;
103 out->max_num_hdmi_frl_outputs = 1;
104 out->max_num_dp2p0_outputs = 2;
105 out->max_num_dp2p0_streams = 4;
110 out->rob_buffer_size_kbytes = 64;
111 out->config_return_buffer_size_in_kbytes = 1792;
112 out->compressed_buffer_segment_size_in_kbytes = 64;
113 out->meta_fifo_size_in_kentries = 32;
114 out->zero_size_buffer_entries = 512;
115 out->pixel_chunk_size_kbytes = 8;
116 out->alpha_pixel_chunk_size_kbytes = 4;
117 out->min_pixel_chunk_size_bytes = 1024;
118 out->meta_chunk_size_kbytes = 2;
119 out->min_meta_chunk_size_bytes = 256;
120 out->writeback_chunk_size_kbytes = 8;
121 out->dpte_buffer_size_in_pte_reqs_luma = 68;
122 out->dpte_buffer_size_in_pte_reqs_chroma = 36;
123 out->dcc_meta_buffer_size_bytes = 6272;
124 out->gpuvm_enable = 1;
125 out->hostvm_enable = 1;
126 out->gpuvm_max_page_table_levels = 1;
127 out->hostvm_max_page_table_levels = 2;
128 out->num_dsc = 4;
129 out->maximum_dsc_bits_per_component = 12;
130 out->maximum_pixels_per_line_per_dsc_unit = 6016;
131 out->dsc422_native_support = 1;
132 out->line_buffer_size_bits = 986880;
133 out->dcc_supported = 1;
134 out->max_line_buffer_lines = 32;
135 out->writeback_interface_buffer_size_kbytes = 90;
136 out->max_num_dpp = 4;
137 out->max_num_otg = 4;
138 out->max_num_hdmi_frl_outputs = 1;
139 out->max_num_dp2p0_outputs = 2;
140 out->max_num_dp2p0_streams = 4;
141 out->max_num_wb = 1;
143 out->max_dchub_pscl_bw_pix_per_clk = 4;
144 out->max_pscl_lb_bw_pix_per_clk = 2;
145 out->max_lb_vscl_bw_pix_per_clk = 4;
146 out->max_vscl_hscl_bw_pix_per_clk = 4;
147 out->max_hscl_ratio = 6;
148 out->max_vscl_ratio = 6;
149 out->max_hscl_taps = 8;
150 out->max_vscl_taps = 8;
151 out->dispclk_ramp_margin_percent = 1.11;
153 out->dppclk_delay_subtotal = 47;
154 out->dppclk_delay_scl = 50;
155 out->dppclk_delay_scl_lb_only = 16;
156 out->dppclk_delay_cnvc_formatter = 28;
157 out->dppclk_delay_cnvc_cursor = 6;
158 out->dispclk_delay_subtotal = 125;
160 out->dynamic_metadata_vm_enabled = false;
161 out->max_inter_dcn_tile_repeaters = 8;
162 out->cursor_buffer_size = 16; // kBytes
163 out->cursor_chunk_size = 2; // kBytes
165 out->writeback_line_buffer_buffer_size = 0;
166 out->writeback_max_hscl_ratio = 1;
167 out->writeback_max_vscl_ratio = 1;
168 out->writeback_min_hscl_ratio = 1;
169 out->writeback_min_vscl_ratio = 1;
170 out->writeback_max_hscl_taps = 1;
171 out->writeback_max_vscl_taps = 1;
172 out->ptoi_supported = 0;
174 out->vblank_nom_default_us = 668; /*not in dml, but in programming guide, hard coded in dml2_translate_ip_params*/
175 out->config_return_buffer_segment_size_in_kbytes = 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/
181 void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)
183 out->dprefclk_mhz = dml2->config.bbox_overrides.dprefclk_mhz;
184 out->xtalclk_mhz = dml2->config.bbox_overrides.xtalclk_mhz;
185 out->pcierefclk_mhz = 100;
186 out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz;
188 out->max_outstanding_reqs = 512;
189 out->pct_ideal_sdp_bw_after_urgent = 100;
190 out->pct_ideal_fabric_bw_after_urgent = 67;
191 out->pct_ideal_dram_bw_after_urgent_pixel_only = 20;
192 out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = 60;
193 out->pct_ideal_dram_bw_after_urgent_vm_only = 30;
194 out->pct_ideal_dram_bw_after_urgent_strobe = 67;
195 out->max_avg_sdp_bw_use_normal_percent = 80;
196 out->max_avg_fabric_bw_use_normal_percent = 60;
197 out->max_avg_dram_bw_use_normal_percent = 15;
198 out->max_avg_dram_bw_use_normal_strobe_percent = 50;
200 out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
201 out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
202 out->urgent_out_of_order_return_per_channel_vm_only_bytes = 4096;
203 out->return_bus_width_bytes = 64;
204 out->dram_channel_width_bytes = 2;
205 out->fabric_datapath_to_dcn_data_return_bytes = 64;
206 out->hostvm_min_page_size_kbytes = 0;
207 out->gpuvm_min_page_size_kbytes = 256;
208 out->phy_downspread_percent = 0.38;
209 out->dcn_downspread_percent = 0.5;
210 out->dispclk_dppclk_vco_speed_mhz = dml2->config.bbox_overrides.disp_pll_vco_speed_mhz;
211 out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64 or 32 MB;
213 out->do_urgent_latency_adjustment = true;
219 out->num_chans = 24;
220 out->round_trip_ping_latency_dcfclk_cycles = 263;
221 out->smn_latency_us = 2;
225 out->num_chans = 8;
226 out->round_trip_ping_latency_dcfclk_cycles = 207;
227 out->smn_latency_us = 0;
232 out->num_chans = 4;
233 out->round_trip_ping_latency_dcfclk_cycles = 106;
234 out->smn_latency_us = 2;
235 out->dispclk_dppclk_vco_speed_mhz = 3600;
241 out->num_chans = dml2->config.bbox_overrides.dram_num_chan;
244 out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes;
248 const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out)
259 p->out_states = out;
445 void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)
449 out->compressed_buffer_segment_size_in_kbytes = in_ip_params->compressed_buffer_segment_size_in_kbytes;
450 out->config_return_buffer_size_in_kbytes = in_ip_params->config_return_buffer_size_in_kbytes;
451 out->cursor_buffer_size = in_ip_params->cursor_buffer_size;
452 out->cursor_chunk_size = in_ip_params->cursor_chunk_size;
453 out->dcc_meta_buffer_size_bytes = in_ip_params->dcc_meta_buffer_size_bytes;
454 out->dcc_supported = in_ip_params->dcc_supported;
455 out->dispclk_delay_subtotal = in_ip_params->dispclk_delay_subtotal;
456 out->dispclk_ramp_margin_percent = in_ip_params->dispclk_ramp_margin_percent;
457 out->dppclk_delay_cnvc_cursor = in_ip_params->dppclk_delay_cnvc_cursor;
458 out->dppclk_delay_cnvc_formatter = in_ip_params->dppclk_delay_cnvc_formatter;
459 out->dppclk_delay_scl = in_ip_params->dppclk_delay_scl;
460 out->dppclk_delay_scl_lb_only = in_ip_params->dppclk_delay_scl_lb_only;
461 out->dppclk_delay_subtotal = in_ip_params->dppclk_delay_subtotal;
462 out->dpte_buffer_size_in_pte_reqs_chroma = in_ip_params->dpte_buffer_size_in_pte_reqs_chroma;
463 out->dpte_buffer_size_in_pte_reqs_luma = in_ip_params->dpte_buffer_size_in_pte_reqs_luma;
464 out->dsc422_native_support = in_ip_params->dsc422_native_support;
465 out->dynamic_metadata_vm_enabled = in_ip_params->dynamic_metadata_vm_enabled;
466 out->gpuvm_enable = in_ip_params->gpuvm_enable;
467 out->gpuvm_max_page_table_levels = in_ip_params->gpuvm_max_page_table_levels;
468 out->hostvm_enable = in_ip_params->hostvm_enable;
469 out->hostvm_max_page_table_levels = in_ip_params->hostvm_max_page_table_levels;
470 out->line_buffer_size_bits = in_ip_params->line_buffer_size_bits;
471 out->maximum_dsc_bits_per_component = in_ip_params->maximum_dsc_bits_per_component;
472 out->maximum_pixels_per_line_per_dsc_unit = in_ip_params->maximum_pixels_per_line_per_dsc_unit;
473 out->max_dchub_pscl_bw_pix_per_clk = in_ip_params->max_dchub_pscl_bw_pix_per_clk;
474 out->max_hscl_ratio = in_ip_params->max_hscl_ratio;
475 out->max_hscl_taps = in_ip_params->max_hscl_taps;
476 out->max_inter_dcn_tile_repeaters = in_ip_params->max_inter_dcn_tile_repeaters;
477 out->max_lb_vscl_bw_pix_per_clk = in_ip_params->max_lb_vscl_bw_pix_per_clk;
478 out->max_line_buffer_lines = in_ip_params->max_line_buffer_lines;
479 out->max_num_dp2p0_outputs = in_ip_params->max_num_dp2p0_outputs;
480 out->max_num_dp2p0_streams = in_ip_params->max_num_dp2p0_streams;
481 out->max_num_dpp = in_ip_params->max_num_dpp;
482 out->max_num_hdmi_frl_outputs = in_ip_params->max_num_hdmi_frl_outputs;
483 out->max_num_otg = in_ip_params->max_num_otg;
484 out->max_num_wb = in_ip_params->max_num_wb;
485 out->max_pscl_lb_bw_pix_per_clk = in_ip_params->max_pscl_lb_bw_pix_per_clk;
486 out->max_vscl_hscl_bw_pix_per_clk = in_ip_params->max_vscl_hscl_bw_pix_per_clk;
487 out->max_vscl_ratio = in_ip_params->max_vscl_ratio;
488 out->max_vscl_taps = in_ip_params->max_vscl_taps;
489 out->meta_chunk_size_kbytes = in_ip_params->meta_chunk_size_kbytes;
490 out->meta_fifo_size_in_kentries = in_ip_params->meta_fifo_size_in_kentries;
491 out->min_meta_chunk_size_bytes = in_ip_params->min_meta_chunk_size_bytes;
492 out->min_pixel_chunk_size_bytes = in_ip_params->min_pixel_chunk_size_bytes;
493 out->num_dsc = in_ip_params->num_dsc;
494 out->pixel_chunk_size_kbytes = in_ip_params->pixel_chunk_size_kbytes;
495 out->ptoi_supported = in_ip_params->ptoi_supported;
496 out->rob_buffer_size_kbytes = in_ip_params->rob_buffer_size_kbytes;
497 out->writeback_chunk_size_kbytes = in_ip_params->writeback_chunk_size_kbytes;
498 out->writeback_interface_buffer_size_kbytes = in_ip_params->writeback_interface_buffer_size_kbytes;
499 out->writeback_line_buffer_buffer_size = in_ip_params->writeback_line_buffer_buffer_size;
500 out->writeback_max_hscl_ratio = in_ip_params->writeback_max_hscl_ratio;
501 out->writeback_max_hscl_taps = in_ip_params->writeback_max_hscl_taps;
502 out->writeback_max_vscl_ratio = in_ip_params->writeback_max_vscl_ratio;
503 out->writeback_max_vscl_taps = in_ip_params->writeback_max_vscl_taps;
504 out->writeback_min_hscl_ratio = in_ip_params->writeback_min_hscl_ratio;
505 out->writeback_min_vscl_ratio = in_ip_params->writeback_min_vscl_ratio;
506 out->zero_size_buffer_entries = in_ip_params->zero_size_buffer_entries;
509 out->config_return_buffer_segment_size_in_kbytes = 64;
510 //out->vblank_nom_default_us = 600;
511 out->vblank_nom_default_us = in_ip_params->VBlankNomDefaultUS;
514 void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out)
518 out->dispclk_dppclk_vco_speed_mhz = in_soc_params->dispclk_dppclk_vco_speed_mhz;
519 out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;
520 out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;
521 out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;
522 out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024;
523 out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024;
524 out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;
525 out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;
526 out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;
527 out->max_avg_dram_bw_use_normal_strobe_percent = in_soc_params->max_avg_dram_bw_use_normal_strobe_percent;
528 out->max_avg_sdp_bw_use_normal_percent = in_soc_params->max_avg_sdp_bw_use_normal_percent;
529 out->max_outstanding_reqs = in_soc_params->max_request_size_bytes;
530 out->num_chans = in_soc_params->num_chans;
531 out->pct_ideal_dram_bw_after_urgent_strobe = in_soc_params->pct_ideal_dram_bw_after_urgent_strobe;
532 out->pct_ideal_dram_bw_after_urgent_vm_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
533 out->pct_ideal_fabric_bw_after_urgent = in_soc_params->pct_ideal_fabric_bw_after_urgent;
534 out->pct_ideal_sdp_bw_after_urgent = in_soc_params->pct_ideal_sdp_bw_after_urgent;
535 out->phy_downspread_percent = in_soc_params->downspread_percent;
536 out->refclk_mhz = 50; // As per hardcoded reference.
537 out->return_bus_width_bytes = in_soc_params->return_bus_width_bytes;
538 out->round_trip_ping_latency_dcfclk_cycles = in_soc_params->round_trip_ping_latency_dcfclk_cycles;
539 out->smn_latency_us = in_soc_params->smn_latency_us;
540 out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
541 out->urgent_out_of_order_return_per_channel_pixel_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_only_bytes;
542 out->urgent_out_of_order_return_per_channel_vm_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_vm_only_bytes;
543 out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
544 out->pct_ideal_dram_bw_after_urgent_pixel_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
545 out->dcn_downspread_percent = in_soc_params->dcn_downspread_percent;
548 void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states)
551 out->num_states = num_states;
553 for (i = 0; i < out->num_states; i++) {
554 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz;
555 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz;
556 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz;
557 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts;
558 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz;
559 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz;
560 out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz;
561 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz;
562 out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz;
563 out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz;
564 out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz;
565 out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us;
566 out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us;
567 out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us;
568 out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us;
569 out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us;
570 out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us;
574 out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us;
575 out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us;
576 //out->state_array[i].sr_exit_z8_time_us = 5.20;
577 //out->state_array[i].sr_enter_plus_exit_z8_time_us = 9.60;
578 out->state_array[i].use_ideal_dram_bw_strobe = true;
579 out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us;
580 out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us;
581 out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us;
582 out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us;
583 out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz;
587 static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
591 out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;
592 out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;
593 out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
594 out->VFrontPorch[location] = in->timing.v_front_porch;
595 out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;
597 out->PixelClock[location] *= 2;
598 out->HTotal[location] = in->timing.h_total;
599 out->VTotal[location] = in->timing.v_total;
600 out->Interlace[location] = in->timing.flags.INTERLACE;
602 out->HBlankEnd[location] = hblank_start
607 out->VBlankEnd[location] = vblank_start
611 out->DRRDisplay[location] = false;
614 static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location,
619 out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC;
620 out->OutputLinkDPLanes[location] = 4; // As per code in dcn20_resource.c
621 out->DSCInputBitPerComponent[location] = 12; // As per code in dcn20_resource.c
626 out->OutputEncoder[location] = dml_dp;
628 out->OutputEncoder[location] = dml_dp2p0;
631 out->OutputEncoder[location] = dml_edp;
636 out->OutputEncoder[location] = dml_hdmi;
639 out->OutputEncoder[location] = dml_dp;
675 out->OutputFormat[location] = dml_444;
676 out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
679 out->OutputFormat[location] = dml_420;
680 out->OutputBpp[location] = (output_bpc * 3.0) / 2;
684 out->OutputFormat[location] = dml_n422;
686 out->OutputFormat[location] = dml_s422;
687 out->OutputBpp[location] = (dml_float_t)output_bpc * 2;
690 out->OutputFormat[location] = dml_444;
691 out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
696 out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;
700 out->OutputMultistreamEn[location] = false;
714 out->OutputLinkDPRate[location] = dml_dp_rate_na;
718 out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;
720 out->AudioSampleLayout[location] = in->audio_info.modes->sample_size;
721 out->AudioSampleRate[location] = in->audio_info.modes->max_bit_rate;
723 out->OutputDisabled[location] = true;
726 static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
728 out->SurfaceWidthY[location] = in->timing.h_addressable;
729 out->SurfaceHeightY[location] = in->timing.v_addressable;
730 out->SurfaceWidthC[location] = in->timing.h_addressable;
731 out->SurfaceHeightC[location] = in->timing.v_addressable;
732 out->PitchY[location] = ((out->SurfaceWidthY[location] + 127) / 128) * 128;
733 out->PitchC[location] = 0;
734 out->DCCEnable[location] = false;
735 out->DCCMetaPitchY[location] = 0;
736 out->DCCMetaPitchC[location] = 0;
737 out->DCCRateLuma[location] = 1.0;
738 out->DCCRateChroma[location] = 1.0;
739 out->DCCFractionOfZeroSizeRequestsLuma[location] = 0;
740 out->DCCFractionOfZeroSizeRequestsChroma[location] = 0;
741 out->SurfaceTiling[location] = dml_sw_64kb_r_x;
742 out->SourcePixelFormat[location] = dml_444_32;
745 static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_project, struct dml_surface_cfg_st *out, unsigned int location, const struct dc_plane_state *in)
747 out->PitchY[location] = in->plane_size.surface_pitch;
748 out->SurfaceHeightY[location] = in->plane_size.surface_size.height;
749 out->SurfaceWidthY[location] = in->plane_size.surface_size.width;
750 out->SurfaceHeightC[location] = in->plane_size.chroma_size.height;
751 out->SurfaceWidthC[location] = in->plane_size.chroma_size.width;
752 out->PitchC[location] = in->plane_size.chroma_pitch;
753 out->DCCEnable[location] = in->dcc.enable;
754 out->DCCMetaPitchY[location] = in->dcc.meta_pitch;
755 out->DCCMetaPitchC[location] = in->dcc.meta_pitch_c;
756 out->DCCRateLuma[location] = 1.0;
757 out->DCCRateChroma[location] = 1.0;
758 out->DCCFractionOfZeroSizeRequestsLuma[location] = in->dcc.independent_64b_blks;
759 out->DCCFractionOfZeroSizeRequestsChroma[location] = in->dcc.independent_64b_blks_c;
763 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle;
770 out->SourcePixelFormat[location] = dml_420_8;
774 out->SourcePixelFormat[location] = dml_420_10;
779 out->SourcePixelFormat[location] = dml_444_64;
783 out->SourcePixelFormat[location] = dml_444_16;
786 out->SourcePixelFormat[location] = dml_444_8;
789 out->SourcePixelFormat[location] = dml_rgbe_alpha;
792 out->SourcePixelFormat[location] = dml_444_32;
821 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
835 out->CursorBPP[location] = dml_cur_32bit;
836 out->CursorWidth[location] = 256;
838 out->GPUVMMinPageSizeKBytes[location] = 256;
840 out->ViewportWidth[location] = width;
841 out->ViewportHeight[location] = height;
842 out->ViewportStationary[location] = false;
843 out->ViewportWidthChroma[location] = 0;
844 out->ViewportHeightChroma[location] = 0;
845 out->ViewportXStart[location] = 0;
846 out->ViewportXStartC[location] = 0;
847 out->ViewportYStart[location] = 0;
848 out->ViewportYStartC[location] = 0;
850 out->ScalerEnabled[location] = false;
851 out->HRatio[location] = 1.0;
852 out->VRatio[location] = 1.0;
853 out->HRatioChroma[location] = 0;
854 out->VRatioChroma[location] = 0;
855 out->HTaps[location] = 1;
856 out->VTaps[location] = 1;
857 out->HTapsChroma[location] = 0;
858 out->VTapsChroma[location] = 0;
859 out->SourceScan[location] = dml_rotation_0;
860 out->ScalerRecoutWidth[location] = width;
862 out->LBBitPerPixel[location] = 57;
864 out->DynamicMetadataEnable[location] = false;
866 out->NumberOfCursors[location] = 1;
867 out->UseMALLForStaticScreen[location] = dml_use_mall_static_screen_disable;
868 out->UseMALLForPStateChange[location] = dml_use_mall_pstate_change_disable;
870 out->DETSizeOverride[location] = 256;
872 out->ScalerEnabled[location] = false;
875 static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context)
879 out->CursorBPP[location] = dml_cur_32bit;
880 out->CursorWidth[location] = 256;
882 out->GPUVMMinPageSizeKBytes[location] = 256;
884 out->ViewportWidth[location] = scaler_data.viewport.width;
885 out->ViewportHeight[location] = scaler_data.viewport.height;
886 out->ViewportWidthChroma[location] = scaler_data.viewport_c.width;
887 out->ViewportHeightChroma[location] = scaler_data.viewport_c.height;
888 out->ViewportXStart[location] = scaler_data.viewport.x;
889 out->ViewportYStart[location] = scaler_data.viewport.y;
890 out->ViewportXStartC[location] = scaler_data.viewport_c.x;
891 out->ViewportYStartC[location] = scaler_data.viewport_c.y;
892 out->ViewportStationary[location] = false;
894 out->ScalerEnabled[location] = scaler_data.ratios.horz.value != dc_fixpt_one.value ||
904 out->LBBitPerPixel[location] = 57;
906 if (out->ScalerEnabled[location] == false) {
907 out->HRatio[location] = 1;
908 out->HRatioChroma[location] = 1;
909 out->VRatio[location] = 1;
910 out->VRatioChroma[location] = 1;
913 out->HRatio[location] = (dml_float_t)scaler_data.ratios.horz.value / (1ULL << 32);
914 out->HRatioChroma[location] = (dml_float_t)scaler_data.ratios.horz_c.value / (1ULL << 32);
915 out->VRatio[location] = (dml_float_t)scaler_data.ratios.vert.value / (1ULL << 32);
916 out->VRatioChroma[location] = (dml_float_t)scaler_data.ratios.vert_c.value / (1ULL << 32);
920 out->HTaps[location] = 1;
921 out->HTapsChroma[location] = 1;
923 out->HTaps[location] = scaler_data.taps.h_taps;
924 out->HTapsChroma[location] = scaler_data.taps.h_taps_c;
927 out->VTaps[location] = 1;
928 out->VTapsChroma[location] = 1;
930 out->VTaps[location] = scaler_data.taps.v_taps;
931 out->VTapsChroma[location] = scaler_data.taps.v_taps_c;
934 out->SourceScan[location] = (enum dml_rotation_angle)in->rotation;
935 out->ScalerRecoutWidth[location] = in->dst_rect.width;
937 out->DynamicMetadataEnable[location] = false;
938 out->DynamicMetadataLinesBeforeActiveRequired[location] = 0;
939 out->DynamicMetadataTransmittedBytes[location] = 0;
941 out->NumberOfCursors[location] = 1;
1189 struct pipe_ctx *out)
1191 memset(&out->rq_regs, 0, sizeof(out->rq_regs));
1192 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size;
1193 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size;
1194 out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size;
1195 out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size;
1196 out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size;
1197 out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size;
1198 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height;
1199 out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear;
1201 out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size;
1202 out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size;
1203 out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size;
1204 out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size;
1205 out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size;
1206 out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size;
1207 out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height;
1208 out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear;
1210 out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode;
1211 out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode;
1212 out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode;
1213 out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode;
1214 out->rq_regs.plane1_base_address = rq_regs->plane1_base_address;
1216 memset(&out->dlg_regs, 0, sizeof(out->dlg_regs));
1217 out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end;
1218 out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end;
1219 out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
1220 out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal;
1221 out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler;
1222 out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler;
1223 out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch;
1224 out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank;
1225 out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank;
1226 out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip;
1227 out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip;
1228 out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq;
1229 out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch;
1230 out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c;
1231 out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l;
1232 out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c;
1233 out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;
1234 out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c;
1235 out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l;
1236 out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c;
1237 out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l;
1238 out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c;
1239 out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l;
1240 out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c;
1241 out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l;
1242 out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c;
1243 out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l;
1244 out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c;
1245 out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l;
1246 out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c;
1247 out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l;
1248 out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c;
1249 out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l;
1250 out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c;
1251 out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank;
1252 out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip;
1253 out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank;
1254 out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip;
1255 out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0;
1256 out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0;
1257 out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1;
1258 out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1;
1259 out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;
1260 out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit;
1261 out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata;
1262 out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta;
1264 memset(&out->ttu_regs, 0, sizeof(out->ttu_regs));
1265 out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm;
1266 out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;
1267 out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank;
1268 out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip;
1269 out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l;
1270 out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c;
1271 out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0;
1272 out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1;
1273 out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l;
1274 out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c;
1275 out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0;
1276 out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1;
1277 out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l;
1278 out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c;
1279 out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0;
1280 out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1;
1281 out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l;
1282 out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c;
1283 out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0;
1284 out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1;