Lines Matching refs:config

49 	for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
54 ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
56 mblk_width = ctx->config.mall_cfg.mblk_width_pixels;
57 mblk_height = bytes_per_pixel == 4 ? mblk_width = ctx->config.mall_cfg.mblk_height_4bpe_pixels : ctx->config.mall_cfg.mblk_height_8bpe_pixels;
80 bytes_in_mall = num_mblks * ctx->config.mall_cfg.mblk_size_bytes;
83 cache_lines_per_plane = bytes_in_mall / ctx->config.mall_cfg.cache_line_size_bytes + 2;
92 total_cache_lines = ctx->config.mall_cfg.max_cab_allocation_bytes / ctx->config.mall_cfg.cache_line_size_bytes;
93 lines_per_way = total_cache_lines / ctx->config.mall_cfg.cache_num_ways;
106 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
125 ctx->config.svp_pstate.callbacks.release_dsc(&context->res_ctx, ctx->config.svp_pstate.callbacks.dc->res_pool, &pipe->stream_res.dsc);
150 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
191 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
202 free_pipes = ctx->config.dcn_pipe_count - num_pipes;
211 * we are forcing SubVP P-State switching on the current config.
237 for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) {
256 ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_NONE && refresh_rate < 120 &&
296 * e.g. For a 2 stream config where the first stream uses one
312 unsigned int min_pipe_split = ctx->config.dcn_pipe_count + 1; // init as max number of pipes + 1
315 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
320 ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_NONE) {
336 if (free_pipes >= min_pipe_split && free_pipes < ctx->config.dcn_pipe_count)
343 * subvp_subvp_schedulable: Determine if SubVP + SubVP config is schedulable
355 * bool - True if the SubVP + SubVP config is schedulable, false otherwise
367 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
375 ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
376 phantom = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);
383 ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us +
384 ctx->config.svp_pstate.subvp_fw_processing_delay_us + 1;
415 * dml2_svp_drr_schedulable: Determine if SubVP + DRR config is schedulable
426 * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config
429 * bool - True if the SubVP + DRR config is schedulable, false otherwise
448 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
457 if (ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe) == SUBVP_MAIN)
461 phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);
466 ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;
493 * subvp_vblank_schedulable: Determine if SubVP + VBLANK config is schedulable
505 * bool - True if the SubVP + VBLANK/DRR config is schedulable, false otherwise
533 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
535 pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);
556 phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, subvp_pipe->stream);
564 ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;
609 for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) {
611 enum mall_stream_type pipe_mall_type = ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe);
664 for (i = 0, pipe_idx = 0; i < ctx->config.dcn_pipe_count; i++) {
677 pstate_width_fw_delay_lines = ((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us +
678 ctx->config.svp_pstate.subvp_pstate_allow_width_us) / 1000000) *
687 phantom_vactive = svp_height + pstate_width_fw_delay_lines + ctx->config.svp_pstate.subvp_swath_height_margin_lines;
718 struct dc_stream_state *phantom_stream = ctx->config.svp_pstate.callbacks.create_phantom_stream(
719 ctx->config.svp_pstate.callbacks.dc,
729 ctx->config.svp_pstate.callbacks.add_phantom_stream(ctx->config.svp_pstate.callbacks.dc,
749 phantom_plane = ctx->config.svp_pstate.callbacks.create_phantom_plane(
750 ctx->config.svp_pstate.callbacks.dc,
775 ctx->config.svp_pstate.callbacks.add_phantom_plane(ctx->config.svp_pstate.callbacks.dc, phantom_stream, phantom_plane, state);
793 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
800 ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {
803 if (!ctx->config.svp_pstate.callbacks.build_scaling_params(pipe)) {
832 if (!ctx->config.svp_pstate.callbacks.remove_phantom_plane(ctx->config.svp_pstate.callbacks.dc, stream, del_planes[i], context))
834 ctx->config.svp_pstate.callbacks.release_phantom_plane(ctx->config.svp_pstate.callbacks.dc, context, del_planes[i]);
846 for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
849 if (pipe->plane_state && pipe->stream && ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(state, pipe) == SUBVP_PHANTOM) {
853 ctx->config.svp_pstate.callbacks.remove_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);
854 ctx->config.svp_pstate.callbacks.release_phantom_stream(ctx->config.svp_pstate.callbacks.dc, state, phantom_stream);
879 if (ctx->config.svp_pstate.force_disable_subvp)
890 for (int i = 0; i < ctx->config.dcn_pipe_count; i++) {
896 ctx->config.svp_pstate.callbacks.build_scaling_params(pipe_ctx);