dc/dml2/display_mode_core.c

5764 								const struct soc_bounding_box_st *soc,
5772 		dml_min3(soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0,
5773 				FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes * soc->pct_ideal_sdp_bw_after_urgent / 100.0,
5774 				DRAMSpeed * soc->num_chans *  soc->dram_channel_width_bytes *
5775 				((use_ideal_dram_bw_strobe && !HostVMEnable) ? soc->pct_ideal_dram_bw_after_urgent_strobe :  soc->pct_ideal_dram_bw_after_urgent_vm_only) / 100.0);
5790 						const struct soc_bounding_box_st *soc,
5798 	dml_float_t IdealSDPPortBandwidth    = soc->return_bus_width_bytes * DCFCLK;
5799 	dml_float_t IdealFabricBandwidth     = FabricClock * soc->fabric_datapath_to_dcn_data_return_bytes;
5800 	dml_float_t IdealDRAMBandwidth       = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes;
5801 	dml_float_t PixelDataOnlyReturnBW    = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100,
5802 												IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100,
5803 												IdealDRAMBandwidth * ((use_ideal_dram_bw_strobe && !HostVMEnable) ? soc->pct_ideal_dram_bw_after_urgent_strobe :
5804 																						soc->pct_ideal_dram_bw_after_urgent_pixel_only) / 100);
5805 	dml_float_t PixelMixedWithVMDataReturnBW = dml_min3(IdealSDPPortBandwidth * soc->pct_ideal_sdp_bw_after_urgent / 100,
5806 													IdealFabricBandwidth * soc->pct_ideal_fabric_bw_after_urgent / 100,
5807 													IdealDRAMBandwidth * ((use_ideal_dram_bw_strobe && !HostVMEnable) ? soc->pct_ideal_dram_bw_after_urgent_strobe :
5808 																							soc->pct_ideal_dram_bw_after_urgent_pixel_and_vm) / 100);
5835 						const struct soc_bounding_box_st *soc,
5841 	dml_float_t IdealDRAMBandwidth       = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes;
5842 	dml_float_t PixelDataOnlyReturnBW    = IdealDRAMBandwidth * ((use_ideal_dram_bw_strobe && !HostVMEnable) ? soc->pct_ideal_dram_bw_after_urgent_strobe :
5843 																						soc->pct_ideal_dram_bw_after_urgent_pixel_only) / 100;
5844 	dml_float_t PixelMixedWithVMDataReturnBW =  IdealDRAMBandwidth * ((use_ideal_dram_bw_strobe && !HostVMEnable) ? soc->pct_ideal_dram_bw_after_urgent_strobe :
5845 																							soc->pct_ideal_dram_bw_after_urgent_pixel_and_vm) / 100;
6232 				CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
6306 																	&mode_lib->ms.soc,
6318 				mode_lib->ms.soc.round_trip_ping_latency_dcfclk_cycles,
6332 				mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
6545 						mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
6641 		s->mSOCParameters.SMNLatency = mode_lib->ms.soc.smn_latency_us;
7050 					mode_lib->ms.soc.dcn_downspread_percent,
7052 					mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz,
7072 					mode_lib->ms.soc.dcn_downspread_percent,
7074 					mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz,
7086 					mode_lib->ms.soc.phy_downspread_percent,
7137 			} else if (RoundToDFSGranularity(mode_lib->ms.MinDPPCLKUsingSingleDPP[k] * (1 + mode_lib->ms.soc.dcn_downspread_percent / 100),
7138 											1, mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz) <= mode_lib->ms.state.dppclk_mhz &&
7204 																							mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz));
7218 					mode_lib->ms.soc.dcn_downspread_percent,
7219 					mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz,
7404 						if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
7413 						if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
7417 						if (mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3.0 / (dml_float_t)s->DSCFormatFactor > (1.0 - mode_lib->ms.soc.dcn_downspread_percent / 100.0) * mode_lib->ms.state.dscclk_mhz) {
7581 			mode_lib->ms.soc.mall_allocated_for_dcn_mbytes,
7682 		CalculateVMRowAndSwath_params->MALLAllocatedForDCN = mode_lib->ms.soc.mall_allocated_for_dcn_mbytes;
7690 		CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
7775 													mode_lib->ms.soc.do_urgent_latency_adjustment,
7825 				mode_lib->ms.soc.return_bus_width_bytes,
7888 	s->ReorderingBytes = (dml_uint_t)(mode_lib->ms.soc.num_chans * dml_max3(mode_lib->ms.soc.urgent_out_of_order_return_per_channel_pixel_only_bytes,
7889 																mode_lib->ms.soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes,
7890 																mode_lib->ms.soc.urgent_out_of_order_return_per_channel_vm_only_bytes));
7951 		UseMinimumDCFCLK_params->ReturnBusWidth = mode_lib->ms.soc.return_bus_width_bytes;
7952 		UseMinimumDCFCLK_params->RoundTripPingLatencyCycles = mode_lib->ms.soc.round_trip_ping_latency_dcfclk_cycles;
7960 		UseMinimumDCFCLK_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
7965 		UseMinimumDCFCLK_params->MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation = mode_lib->ms.soc.max_avg_sdp_bw_use_normal_percent;
7966 		UseMinimumDCFCLK_params->PercentOfIdealSDPPortBWReceivedAfterUrgLatency = mode_lib->ms.soc.pct_ideal_sdp_bw_after_urgent;
8004 		mode_lib->ms.ReturnBWPerState[j] = dml_get_return_bw_mbps(&mode_lib->ms.soc, mode_lib->ms.state.use_ideal_dram_bw_strobe,
8007 		mode_lib->ms.ReturnDRAMBWPerState[j] = dml_get_return_dram_bw_mbps(&mode_lib->ms.soc, mode_lib->ms.state.use_ideal_dram_bw_strobe,
8015 			(mode_lib->ms.soc.round_trip_ping_latency_dcfclk_cycles + 32) / mode_lib->ms.DCFCLKState[j] + s->ReorderingBytes / mode_lib->ms.ReturnBWPerState[j]) {
8030 		mode_lib->ms.support.MaxTotalVerticalActiveAvailableBandwidth[j] = dml_min3(mode_lib->ms.soc.return_bus_width_bytes * mode_lib->ms.DCFCLKState[j] * mode_lib->ms.soc.max_avg_sdp_bw_use_normal_percent / 100.0,
8031 																	mode_lib->ms.state.fabricclk_mhz * mode_lib->ms.soc.fabric_datapath_to_dcn_data_return_bytes * mode_lib->ms.soc.max_avg_fabric_bw_use_normal_percent / 100.0,
8032 																	mode_lib->ms.state.dram_speed_mts * mode_lib->ms.soc.num_chans * mode_lib->ms.soc.dram_channel_width_bytes *
8034 																	mode_lib->ms.soc.max_avg_dram_bw_use_normal_strobe_percent : mode_lib->ms.soc.max_avg_dram_bw_use_normal_percent) / 100.0);
8268 	mode_lib->ms.ReturnBW = dml_get_return_bw_mbps(&mode_lib->ms.soc,
8316 	dml_print_soc_bounding_box(&mode_lib->ms.soc);
8344 									mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz));
8355 																					mode_lib->ms.soc.dcn_downspread_percent,
8357 																					mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz,
8393 					mode_lib->ms.soc.dcn_downspread_percent,
8394 					mode_lib->ms.soc.dispclk_dppclk_vco_speed_mhz,
8565 			mode_lib->ms.soc.return_bus_width_bytes,
8584 				locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 12 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
8586 				locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 6 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
8588 				locals->DSCCLK_calculated[k] = mode_lib->ms.cache_display_cfg.output.PixelClockBackEnd[k] / 3 / s->DSCFormatFactor / (1 - mode_lib->ms.soc.dcn_downspread_percent / 100);
8615 		mode_lib->ms.soc.mall_allocated_for_dcn_mbytes,
8694 	CalculateVMRowAndSwath_params->MALLAllocatedForDCN = mode_lib->ms.soc.mall_allocated_for_dcn_mbytes;
8702 	CalculateVMRowAndSwath_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
8753 	s->ReorderBytes = (dml_uint_t)(mode_lib->ms.soc.num_chans * dml_max3(
8754 			mode_lib->ms.soc.urgent_out_of_order_return_per_channel_pixel_only_bytes,
8755 			mode_lib->ms.soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes,
8756 			mode_lib->ms.soc.urgent_out_of_order_return_per_channel_vm_only_bytes));
8758 	s->VMDataOnlyReturnBW = dml_get_return_bw_mbps_vm_only(&mode_lib->ms.soc,
8767 	dml_print("DML::%s: mode_lib->ms.soc.return_bus_width_bytes = %u\n", __func__, mode_lib->ms.soc.return_bus_width_bytes);
8769 	dml_print("DML::%s: mode_lib->ms.soc.fabric_datapath_to_dcn_data_return_bytes = %u\n", __func__, mode_lib->ms.soc.fabric_datapath_to_dcn_data_return_bytes);
8770 	dml_print("DML::%s: mode_lib->ms.soc.pct_ideal_sdp_bw_after_urgent = %f\n", __func__, mode_lib->ms.soc.pct_ideal_sdp_bw_after_urgent);
8772 	dml_print("DML::%s: mode_lib->ms.soc.num_chans = %u\n", __func__, mode_lib->ms.soc.num_chans);
8773 	dml_print("DML::%s: mode_lib->ms.soc.dram_channel_width_bytes = %u\n", __func__, mode_lib->ms.soc.dram_channel_width_bytes);
8794 			mode_lib->ms.soc.round_trip_ping_latency_dcfclk_cycles,
8808 			mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
8858 												mode_lib->ms.soc.do_urgent_latency_adjustment,
8998 			CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024;
9243 						mode_lib->ms.soc.hostvm_min_page_size_kbytes * 1024,
9396 		s->mmSOCParameters.SMNLatency = mode_lib->ms.soc.smn_latency_us;
10042 	mode_lib->ms.soc = mode_lib->soc;