Lines Matching refs:clk_table
258 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
267 struct clk_limit_table *clk_table = &bw_params->clk_table;
279 ASSERT(clk_table->num_entries);
282 for (i = 0; i < clk_table->num_entries; ++i) {
283 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
284 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
285 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
286 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
289 for (i = 0; i < clk_table->num_entries; i++) {
294 clk_table->entries[i].dcfclk_mhz) {
299 if (clk_table->num_entries == 1) {
307 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
308 if (clk_table->num_entries == 1 &&
317 clk_table->entries[i].fclk_mhz;
319 clk_table->entries[i].socclk_mhz;
321 if (clk_table->entries[i].memclk_mhz &&
322 clk_table->entries[i].wck_ratio)
324 clk_table->entries[i].memclk_mhz * 2 *
325 clk_table->entries[i].wck_ratio;
351 if (clk_table->num_entries)
352 dcn3_51_soc.num_states = clk_table->num_entries;
388 if (clk_table->num_entries > 2) {
390 for (i = 0; i < clk_table->num_entries; i++) {
392 clk_table->num_entries;
404 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
408 clk_table->num_entries;
410 clk_table->num_entries;
412 clk_table->num_entries;
414 clk_table->num_entries;
416 clk_table->num_entries;
418 clk_table->num_entries;
420 clk_table->num_entries;