Lines Matching refs:clk_table
257 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
266 struct clk_limit_table *clk_table = &bw_params->clk_table;
278 ASSERT(clk_table->num_entries);
281 for (i = 0; i < clk_table->num_entries; ++i) {
282 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
283 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
284 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
285 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
288 for (i = 0; i < clk_table->num_entries; i++) {
293 clk_table->entries[i].dcfclk_mhz) {
298 if (clk_table->num_entries == 1) {
306 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
307 if (clk_table->num_entries == 1 &&
316 clk_table->entries[i].fclk_mhz;
318 clk_table->entries[i].socclk_mhz;
320 if (clk_table->entries[i].memclk_mhz &&
321 clk_table->entries[i].wck_ratio)
323 clk_table->entries[i].memclk_mhz * 2 *
324 clk_table->entries[i].wck_ratio;
350 if (clk_table->num_entries)
351 dcn3_51_soc.num_states = clk_table->num_entries;
387 if (clk_table->num_entries > 2) {
389 for (i = 0; i < clk_table->num_entries; i++) {
391 clk_table->num_entries;
403 clk_table->entries[i].memclk_mhz * clk_table->entries[i].wck_ratio;
407 clk_table->num_entries;
409 clk_table->num_entries;
411 clk_table->num_entries;
413 clk_table->num_entries;
415 clk_table->num_entries;
417 clk_table->num_entries;
419 clk_table->num_entries;