dml/dcn32/dcn32_fpu.c

191 	uint16_t min_uclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
192 	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
202 		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
204 	if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
205 		setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
243 		clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
245 		clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
247 		clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
249 		clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
2420 		dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
2471 			int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1;
2474 				dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16;
2631 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2632 			max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2633 		if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
2634 			max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2635 		if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
2636 			max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2637 		if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2638 			max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2639 		if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2640 			max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2641 		if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2642 			max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2643 		if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
2644 			max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2654 		bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
2656 		bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
2658 		bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz;
2660 		bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16;
2777 		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz)
2778 			max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2779 		if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz)
2780 			max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2781 		if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz)
2782 			max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
2783 		if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz)
2784 			max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2785 		if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz)
2786 			max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2787 		if (bw_params->clk_table.entries[i].phyclk_mhz > max_clk_data.phyclk_mhz)
2788 			max_clk_data.phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2789 		if (bw_params->clk_table.entries[i].dtbclk_mhz > max_clk_data.dtbclk_mhz)
2790 			max_clk_data.dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
2792 		if (bw_params->clk_table.entries[i].memclk_mhz > 0) {
2794 			if (bw_params->clk_table.entries[i].memclk_mhz <= bw_params->dc_mode_limit.memclk_mhz)
2797 		if (bw_params->clk_table.entries[i].fclk_mhz > 0) {
2799 			if (bw_params->clk_table.entries[i].fclk_mhz <= bw_params->dc_mode_limit.fclk_mhz)
2802 		if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) {
2804 			if (bw_params->clk_table.entries[i].dcfclk_mhz <= bw_params->dc_mode_limit.dcfclk_mhz)
2815 		bw_params->clk_table.num_entries_per_clk.num_memclk_levels = num_uclk_dpms;
2816 		bw_params->clk_table.num_entries_per_clk.num_fclk_levels = num_fclk_dpms;
2819 	if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)
2820 		min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;
2869 		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2880 			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2934 			if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
2935 				table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
2945 				if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
2946 					table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
3001  * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
3105 	if (bw_params->clk_table.entries[0].memclk_mhz) {
3121 				if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
3122 					max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
3123 				if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
3124 						bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
3125 					min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
3126 				if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
3127 					max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
3128 				if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
3129 					max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
3130 				if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
3131 					max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
3160 			num_uclk_states = bw_params->clk_table.num_entries;
3164 				dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
3166 				if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
3167 					optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
3176 								bw_params->clk_table.entries[j].memclk_mhz * 16;
3192 						dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3207 				dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
3224 					if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
3227 						dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3229 				} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
3230 					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;
3233 				if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
3236 					dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
3259 	if (dc->clk_mgr->bw_params->clk_table.num_entries > 1) {
3262 		dc->dml2_options.bbox_overrides.clks_table.num_states = dc->clk_mgr->bw_params->clk_table.num_entries;
3265 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels;
3268 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels;
3271 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3274 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels;
3277 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels;
3280 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
3283 			dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
3285 		for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels; i++) {
3286 			if (dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz)
3288 					dc->clk_mgr->bw_params->clk_table.entries[i].dcfclk_mhz;
3291 		for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_fclk_levels; i++) {
3292 			if (dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz)
3294 					dc->clk_mgr->bw_params->clk_table.entries[i].fclk_mhz;
3297 		for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
3298 			if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
3300 					dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
3303 		for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_socclk_levels; i++) {
3304 			if (dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz)
3306 					dc->clk_mgr->bw_params->clk_table.entries[i].socclk_mhz;
3309 		for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels; i++) {
3310 			if (dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz)
3312 					dc->clk_mgr->bw_params->clk_table.entries[i].dtbclk_mhz;
3315 		for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; i++) {
3316 			if (dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz) {
3318 					dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
3320 					dc->clk_mgr->bw_params->clk_table.entries[i].dispclk_mhz;
3539 		int num_mclk_levels = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels;
3541 		if (context->bw_ctx.dml.vba.DRAMSpeed <= dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 16 &&
3543 			context->bw_ctx.dml.vba.DRAMSpeed = dc->clk_mgr->bw_params->clk_table.entries[1].memclk_mhz * 16;