dml/dcn32/dcn32_fpu.c

279 							    int vlevel)
284 	enum clock_change_support temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
290 			vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
293 		dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
296 		if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported &&
298 			vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_support;
300 		if (vlevel < context->bw_ctx.dml.vba.soc.num_states &&
301 				vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported)
478 	unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel;
479 	unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
480 	unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel];
506 	pipes[0].clks_cfg.voltage = vlevel;
1025  * @vlevel: Voltage level calculated by DML
1036 				int vlevel)
1062 		if (vba->ActiveDRAMClockChangeLatencyMarginPerState[vlevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&
1078 		else if (dcn32_subvp_vblank_admissable(dc, context, vlevel))
1080 	} else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp &&
1393 		unsigned int *vlevel,
1410 		*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, new_vlevel, split, merge);
1411 		context->bw_ctx.dml.vba.VoltageLevel = *vlevel;
1434 				   int *vlevel,
1461 	*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1462 	/* This may adjust vlevel and maxMpcComb */
1463 	if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1464 		*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1465 		vba->VoltageLevel = *vlevel;
1483 		(*vlevel == context->bw_ctx.dml.soc.num_states || (vba->DRAMSpeedPerState[*vlevel] != vba->DRAMSpeedPerState[0] &&
1484 				vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) ||
1485 	    vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported ||
1488 		vlevel_temp = *vlevel;
1492 			/* For the case where *vlevel = num_states, bandwidth validation has failed for this config.
1499 			if (*vlevel == context->bw_ctx.dml.soc.num_states &&
1509 				*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1518 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1520 			/* Check that vlevel requested supports pstate or not
1521 			 * if not, select the lowest vlevel that supports it
1523 			for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) {
1525 					*vlevel = i;
1530 			if (*vlevel < context->bw_ctx.dml.soc.num_states
1531 			    && subvp_validate_static_schedulability(dc, context, *vlevel))
1534 				// For SubVP + DRR cases, we can force the lowest vlevel that supports the mode
1536 					/* find lowest vlevel that supports the config */
1537 					for (i = *vlevel; i >= 0; i--) {
1539 							*vlevel = i;
1548 		if (vba->DRAMSpeedPerState[*vlevel] >= vba->DRAMSpeedPerState[vlevel_temp])
1556 			vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported;
1559 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1560 			/* This may adjust vlevel and maxMpcComb */
1561 			if (*vlevel < context->bw_ctx.dml.soc.num_states) {
1562 				*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1563 				vba->VoltageLevel = *vlevel;
1577 			*vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge);
1578 			vba->VoltageLevel = *vlevel;
1587 				dc, context, pipes, split, merge, vlevel, *pipe_cnt);
1639 				       int pipe_cnt, int vlevel)
1658 			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1668 	context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000;
1669 	if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported)
1674 	usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1772 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz
1774 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz
2142 	int vlevel = context->bw_ctx.dml.soc.num_states;
2168 		if (!dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge,
2175 			(vlevel == context->bw_ctx.dml.soc.num_states ||
2176 				vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) {
2191 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2195 		if (vlevel < context->bw_ctx.dml.soc.num_states) {
2198 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2200 			vba->VoltageLevel = vlevel;
2206 	if (vlevel == context->bw_ctx.dml.soc.num_states)
2239 		int flag_vlevel = vlevel;
2254 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2256 		if (vlevel == context->bw_ctx.dml.soc.num_states) {
2267 					vlevel = i;
2278 	*vlevel_out = vlevel;
2295 				int vlevel)
2299 	double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2302 	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2319 			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2325 						context, pipes, pipe_cnt, vlevel);
2337 		dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2340 			context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp;
2351 			pstate_en && vlevel != 0)) {
2361 				context, pipes, pipe_cnt, vlevel);
2379 			if (vlevel_temp < vlevel) {
2380 				vlevel = vlevel_temp;
2382 				dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2384 				context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] = dm_dram_clock_change_vblank;
2396 				dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2479 	pipes[0].clks_cfg.voltage = vlevel;
2481 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2494 		if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
2600 	dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);