dml/dcn32/dcn32_fpu.c

277 							    display_e2e_pipe_params_st *pipes,
293 		dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
295 		/* for subvp + DRR case, if subvp pipes are still present we support pstate */
322  * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
326  * @pipes: [in] DML pipe params array
329  * This function must be called AFTER the phantom pipes are added to context
330  * and run through DML (so that the DLG params for the phantom pipes can be
331  * populated), and BEFORE we program the timing for the phantom pipes.
335 					      display_e2e_pipe_params_st *pipes,
349 			pipes[pipe_idx].pipe.dest.vstartup_start =
350 				get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
351 			pipes[pipe_idx].pipe.dest.vupdate_offset =
352 				get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
353 			pipes[pipe_idx].pipe.dest.vupdate_width =
354 				get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
355 			pipes[pipe_idx].pipe.dest.vready_offset =
356 				get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
357 			pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest;
450  * @pipes: DML pipe params
451  * @pipe_cnt: number of DML pipes
470 				     display_e2e_pipe_params_st *pipes,
506 	pipes[0].clks_cfg.voltage = vlevel;
507 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
508 	pipes[0].clks_cfg.socclk_mhz = socclk;
515 	phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) +
527 	phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
549  * dcn32_get_num_free_pipes - Calculate number of free pipes
556  * Return: Number of free pipes available in the context
583  * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
585  * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
589  * The number of pipes used for the chosen surface must be less than or equal to the
590  * number of free pipes available.
660  * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP.
664  * This function returns true if there are enough free pipes
665  * to create the required phantom pipes for any given stream
669  * pipe and the second stream uses 2 pipes (i.e. pipe split),
675  * True if there are enough free pipes to assign phantom pipes to at least one
676  * stream that does not already have phantom pipes assigned. Otherwise false.
681 	unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1
687 		// Find the minimum pipe split count for non SubVP pipes
717  * 1. Find longest microschedule length (in us) between the two SubVP pipes
719  * pipes still allows for the maximum microschedule to fit in the active
720  * region for both pipes.
738 		/* Loop to calculate the maximum microschedule time between the two SubVP pipes,
758 			// Maximum 2 SubVP pipes
977  * - All SubVP pipes are < 120Hz OR
978  * - All SubVP pipes are >= 120hz
1312 	 * optimize power consumption when there are not enough free pipes to
1390 		display_e2e_pipe_params_st *pipes,
1401 		cur_policy[i] = pipes[i].pipe.dest.odm_combine_policy;
1402 		pipes[i].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1405 	new_vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1414 			pipes[i].pipe.dest.odm_combine_policy = cur_policy[i];
1433 				   display_e2e_pipe_params_st *pipes,
1461 	*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1474 	/* Conditions for setting up phantom pipes for SubVP:
1477 	 * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?)
1493 			 * Adding phantom pipes won't change the validation result, so change the DML input param
1494 			 * for P-State support before adding phantom pipes and recalculating the DML result.
1509 				*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1512 			dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx);
1514 			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1517 			pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0);
1518 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1552 		// remove phantom pipes and repopulate dml pipes
1557 			*pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false);
1559 			*vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt);
1567 			dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);
1573 			 * When setting up SubVP config, all pipes are merged before attempting to
1574 			 * add phantom pipes. If pipe split (ODM / MPC) is required, both the main
1575 			 * and phantom pipes will be split in the regular pipe splitting sequence.
1579 			// Note: We can't apply the phantom pipes to hardware at this time. We have to wait
1587 				dc, context, pipes, split, merge, vlevel, *pipe_cnt);
1638 				       display_e2e_pipe_params_st *pipes,
1649 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1680 	unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt);
1697 		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt,
1699 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1701 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,
1703 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,
1711 			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt,
1716 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1717 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1719 			context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1722 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
1724 		context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1732 		/* count from active, top pipes per plane only */
1792 				&context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes,
1796 				&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1827 	 * May need to fix pipes getting tossed from 1 opp to another on flip
1949 		/* merge pipes if necessary */
1953 			/*skip pipes that don't need merging*/
1957 			/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1970 						/* when merging an ODM pipes, the bottom MPC pipe must now point to
2132 				display_e2e_pipe_params_st *pipes,
2147 	ASSERT(pipes);
2148 	if (!pipes)
2151 	/* For each full update, remove all existing phantom pipes first */
2157 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2164 	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
2168 		if (!dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge,
2191 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2242 		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2244 			dcn32_update_dml_pipes_odm_policy_based_on_context(dc, context, pipes);
2246 		/* repopulate_pipes = 1 means the pipes were either split or merged. In this case
2249 		 * pipe split check again after this call (pipes are already split / merged).
2254 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2293 				display_e2e_pipe_params_st *pipes,
2325 						context, pipes, pipe_cnt, vlevel);
2337 		dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2361 				context, pipes, pipe_cnt, vlevel);
2378 			dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel_temp, false);
2396 				dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
2414 	pipes[0].clks_cfg.voltage = vlevel_temp;
2415 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2416 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2424 	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2425 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2426 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2427 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2428 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2429 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2430 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2431 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2432 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2433 	context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2449 	pipes[0].clks_cfg.voltage = vlevel_temp;
2450 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2451 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz;
2459 	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2460 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2461 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2462 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2463 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2464 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2465 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2466 	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2467 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2468 	context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2479 	pipes[0].clks_cfg.voltage = vlevel;
2480 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;
2481 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2484 		pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;
2520 	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2521 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2522 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2523 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2524 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2525 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2526 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2527 	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2532 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2533 	context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2545 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2559 		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2560 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2561 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2562 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2563 		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2564 		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2565 		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2566 		context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2567 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2568 		context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2578 		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2579 		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2582 			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2583 			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2585 		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2586 			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2587 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2588 			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2600 	dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3351 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
3356 	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
3357 	pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;