dml/dcn32/dcn32_fpu.c

363 static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
370 	memory_bw_kbytes_sec = entry->dram_speed_mts *
375 	fabric_bw_kbytes_sec = entry->fabricclk_mhz *
379 	sdp_bw_kbytes_sec = entry->dcfclk_mhz *
394 static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
396 	if (entry->dcfclk_mhz > 0) {
397 		float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
399 		entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
400 		entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
402 	} else if (entry->fabricclk_mhz > 0) {
403 		float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
405 		entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
406 		entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
408 	} else if (entry->dram_speed_mts > 0) {
409 		float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
412 		entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
413 		entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
419 				    struct _vcs_dpi_voltage_scaling_st *entry)
427 		table[0] = *entry;
430 		while (entry->net_bw_in_kbytes_sec > table[index].net_bw_in_kbytes_sec) {
439 		table[index] = *entry;
2503 			/* find largest table entry that is lower than dram speed,
2785 	struct _vcs_dpi_voltage_scaling_st entry = {0};
2862 	entry.dispclk_mhz = max_clk_data.dispclk_mhz;
2863 	entry.dscclk_mhz = max_clk_data.dispclk_mhz / 3;
2864 	entry.dppclk_mhz = max_clk_data.dppclk_mhz;
2865 	entry.dtbclk_mhz = max_clk_data.dtbclk_mhz;
2866 	entry.phyclk_mhz = max_clk_data.phyclk_mhz;
2867 	entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
2868 	entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
2872 		entry.dcfclk_mhz = dcfclk_sta_targets[i];
2873 		entry.fabricclk_mhz = 0;
2874 		entry.dram_speed_mts = 0;
2876 		get_optimal_ntuple(&entry);
2877 		entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2878 		insert_entry_into_table_sorted(table, num_entries, &entry);
2882 	entry.dcfclk_mhz = max_clk_data.dcfclk_mhz;
2883 	entry.fabricclk_mhz = 0;
2884 	entry.dram_speed_mts = 0;
2886 	get_optimal_ntuple(&entry);
2887 	entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2888 	insert_entry_into_table_sorted(table, num_entries, &entry);
2892 		entry.dcfclk_mhz = 0;
2893 		entry.fabricclk_mhz = 0;
2894 		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
2896 		get_optimal_ntuple(&entry);
2897 		entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2898 		insert_entry_into_table_sorted(table, num_entries, &entry);
2904 			entry.dcfclk_mhz = 0;
2905 			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
2906 			entry.dram_speed_mts = 0;
2908 			get_optimal_ntuple(&entry);
2909 			entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2910 			insert_entry_into_table_sorted(table, num_entries, &entry);
2915 		entry.dcfclk_mhz = 0;
2916 		entry.fabricclk_mhz = max_clk_data.fclk_mhz;
2917 		entry.dram_speed_mts = 0;
2919 		get_optimal_ntuple(&entry);
2920 		entry.net_bw_in_kbytes_sec = calculate_net_bw_in_kbytes_sec(&entry);
2921 		insert_entry_into_table_sorted(table, num_entries, &entry);
2936 	// Insert entry with all max dc limits without bandwidth matching
2938 		struct _vcs_dpi_voltage_scaling_st max_dc_limits_entry = entry;