dml/dcn32/dcn32_fpu.c

270  * Finds dummy_latency_index when MCLK switching using firmware based
283 	int dummy_latency_index = 0;
288 	while (dummy_latency_index < max_latency_table_entries) {
292 				dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
304 		dummy_latency_index++;
307 	if (dummy_latency_index == max_latency_table_entries) {
308 		ASSERT(dummy_latency_index != max_latency_table_entries);
312 		 * Here we reset dummy_latency_index to 3, because it is
315 		dummy_latency_index = max_latency_table_entries - 1;
318 	return dummy_latency_index;
2304 	unsigned int dummy_latency_index = 0;
2324 		dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2330 		if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2333 					dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2360 			dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc,
2366 			 * newly found dummy_latency_index
2373 			if (context->bw_ctx.dml.soc.fclk_change_latency_us < dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us) {
2376 						dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2506 			for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--)
2508 					dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
2513 			dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
2598 				dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;