dml/dcn303/dcn303_fpu.c

112 struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = {
173 	bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans *
174 		dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100);
175 	bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans *
176 		dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100);
182 		(dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes *
183 				(dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
187 		(dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
208 		dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
211 		dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
213 	dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
230 			max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz;
232 			max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz;
234 			max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz;
236 			max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz;
313 		dcn3_03_soc.num_states = num_states;
314 		for (i = 0; i < dcn3_03_soc.num_states; i++) {
315 			dcn3_03_soc.clock_limits[i].state = i;
316 			dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
317 			dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
318 			dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
321 			dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
322 			dcn3_03_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;
323 			dcn3_03_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;
326 				dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz;
328 				dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
330 				dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
332 				dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
333 			/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
335 			dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
336 			dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
339 		if (dcn3_03_soc.num_chans <= 4) {
340 			for (i = 0; i < dcn3_03_soc.num_states; i++) {
341 				if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700)
344 				if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) {
345 					dcn3_03_soc.clock_limits[i].dcfclk_mhz = 100;
346 					dcn3_03_soc.clock_limits[i].fabricclk_mhz = 100;
352 		dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
354 			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
363 		dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
366 		dcn3_03_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
369 		dcn3_03_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;