dml/dcn301/dcn301_fpu.c

31 #include "dml/dcn20/dcn20_fpu.h"
295 		struct display_mode_lib *dml,
299 	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
301 	ASSERT(vlevel < dml->soc.num_states);
304 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
305 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
307 	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
308 	dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
309 	dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
311 	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
312 	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
313 	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
314 	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
315 	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
316 	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
317 	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
318 	wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
319 	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
378 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
385 	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
435 						&context->bw_ctx.dml, pipes, pipe_cnt);
440 						&context->bw_ctx.dml, pipes, pipe_cnt);
445 						&context->bw_ctx.dml, pipes, pipe_cnt);
451 						&context->bw_ctx.dml, pipes, pipe_cnt);
457 		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
458 		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
461 			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
462 			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;