dml/dcn30/dcn30_fpu.c

383 		int vlevel)
387 	double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
388 	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
406 				context, pipes, pipe_cnt, vlevel);
414 			dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);
416 			dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
417 			pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
424 	pipes[0].clks_cfg.voltage = vlevel;
426 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
433 		if (vlevel == 0) {
450 	pipes[0].clks_cfg.voltage = vlevel;
486 		if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] ==
582 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
687  * @vlevel: Voltage level calculated by DML
695 							    int vlevel)
705 		dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);