Lines Matching refs:clk_table
2289 vlevel_max = bw_params->clk_table.num_entries - 1;
2373 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
2379 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
2380 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
2381 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
2382 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
2392 for (i = clk_table->num_entries; i > 1; i--)
2393 clk_table->entries[i] = clk_table->entries[i-1];
2394 clk_table->entries[1] = clk_table->entries[0];
2395 clk_table->num_entries++;
2404 struct clk_limit_table *clk_table = &bw_params->clk_table;
2414 ASSERT(clk_table->num_entries);
2418 for (i = 0; i < clk_table->num_entries; i++) {
2421 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2427 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */
2432 s[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2433 s[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2434 s[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
2435 s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
2451 if (clk_table->num_entries) {
2452 dcn2_1_soc.num_states = clk_table->num_entries + 1;
2454 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);