dml/dcn20/dcn20_fpu.c

1144 				int vlevel)
1164 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
1218 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
1219 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
1225 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
1732 			int vlevel,
1744 		pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1748 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1757 					context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1788 	pipes[0].clks_cfg.voltage = vlevel;
1789 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1790 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1793 	if (vlevel < 1) {
1807 	if (vlevel < 2) {
1820 	if (vlevel < 3) {
1833 	pipes[0].clks_cfg.voltage = vlevel;
1834 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
1835 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2033 	int vlevel = 0;
2040 	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2055 	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2056 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2140 			     int vlevel,
2148 		v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] *= 2;
2150 		v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2204 static void calculate_wm_set_for_vlevel(int vlevel,
2213 	ASSERT(vlevel < dml->soc.num_states);
2215 	pipes[0].clks_cfg.voltage = vlevel;
2216 	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
2217 	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
2242 	int vlevel, vlevel_max;
2295 		vlevel = 0;
2297 		vlevel = vlevel_max;
2298 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
2302 	vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
2303 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
2307 	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
2308 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
2313 	vlevel = MIN(vlevel_req, vlevel_max);
2314 	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
2325 	int vlevel = 0;
2337 	out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
2352 	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
2353 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);