Lines Matching defs:dc
127 void dcn10_resource_construct_fp(struct dc *dc)
130 if (dc->ctx->dce_version == DCN_VERSION_1_01) {
131 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
132 struct dcn_ip_params *dcn_ip = dc->dcn_ip;
133 struct display_mode_lib *dml = &dc->dml;
140 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
141 dc->dcn_soc->urgent_latency = 3;
142 dc->debug.disable_dmcu = true;
143 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
146 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
147 ASSERT(dc->dcn_soc->number_of_channels < 3);
148 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
149 dc->dcn_soc->number_of_channels = 2;
151 if (dc->dcn_soc->number_of_channels == 1) {
152 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
153 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
154 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
155 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
156 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev))
157 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;