Lines Matching defs:pipe
302 const struct pipe_ctx *pipe,
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
309 pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
311 input->src.hsplit_grp = pipe->pipe_idx;
312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {
314 } else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
323 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
334 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
337 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;
339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;
348 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
350 switch (pipe->plane_state->rotation) {
365 switch (pipe->plane_state->format) {
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
406 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;
407 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
408 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
409 input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
412 switch (pipe->plane_res.scl_data.lb_params.depth) {
422 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
423 + pipe->stream->timing.v_border_bottom;
425 input->dest.recout_width = pipe->plane_res.scl_data.recout.width;
426 input->dest.recout_height = pipe->plane_res.scl_data.recout.height;
428 input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width;
429 input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height;
431 input->dest.htotal = pipe->stream->timing.h_total;
432 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
434 - pipe->stream->timing.h_addressable
435 - pipe->stream->timing.h_border_left
436 - pipe->stream->timing.h_border_right;
438 input->dest.vtotal = pipe->stream->timing.v_total;
439 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;
441 - pipe->stream->timing.v_addressable
442 - pipe->stream->timing.v_border_bottom
443 - pipe->stream->timing.v_border_top;
444 input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
455 struct pipe_ctx *pipe,
459 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
460 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
461 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
462 struct _vcs_dpi_display_rq_params_st *rq_param = &pipe->dml_rq_param;
463 struct _vcs_dpi_display_dlg_sys_params_st *dlg_sys_param = &pipe->dml_dlg_sys_param;
464 struct _vcs_dpi_display_e2e_pipe_params_st *input = &pipe->dml_input;
493 pipe_ctx_to_e2e_pipe_params(pipe, &input->pipe);
507 dml1_rq_dlg_get_rq_params(dml, rq_param, &input->pipe.src);
519 pipe->plane_state->flip_immediate);
684 * disable optional pipe split by lower dispclk bounding box
696 * force enabling pipe split by lower dpp clock for DPM0 to just
697 * below the specify pixel_rate, so bw calc would split pipe.
710 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
713 * Workaround for avoiding pipe-split in cases where we'd split
717 if (pipe->plane_state &&
718 (pipe->plane_state->dst_rect.width <= 16 ||
719 pipe->plane_state->dst_rect.height <= 16 ||
720 pipe->plane_state->src_rect.width <= 16 ||
721 pipe->plane_state->src_rect.height <= 16)) {
894 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
896 if (!pipe->stream)
899 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
905 v->htotal[input_idx] = pipe->stream->timing.h_total;
906 v->vtotal[input_idx] = pipe->stream->timing.v_total;
907 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
908 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
909 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
911 - pipe->stream->timing.v_front_porch;
912 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
913 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
915 if (!pipe->plane_state) {
920 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
921 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
942 v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;
943 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
944 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
945 v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
946 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
947 if (pipe->plane_state->rotation % 2 == 0) {
948 int viewport_end = pipe->plane_res.scl_data.viewport.width
949 + pipe->plane_res.scl_data.viewport.x;
950 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
951 + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
955 - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
958 - pipe->plane_res.scl_data.viewport.x;
960 int viewport_end = pipe->plane_res.scl_data.viewport.height
961 + pipe->plane_res.scl_data.viewport.y;
962 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
963 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
967 - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
970 - pipe->plane_res.scl_data.viewport.y;
972 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
973 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
976 if (pipe->plane_state->rotation % 2 == 0) {
977 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
979 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
982 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
984 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
993 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
1004 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
1008 pipe->plane_state->format);
1010 pipe->plane_state->tiling_info.gfx9.swizzle);
1011 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
1012 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
1013 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
1014 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
1015 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
1025 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
1030 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
1032 v->output[input_idx] = pipe->stream->signal ==
1036 switch (pipe->stream->timing.display_color_depth) {
1061 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1200 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1202 /* skip inactive pipe */
1203 if (!pipe->stream)
1206 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1209 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1210 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1211 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1212 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1214 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1215 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1216 vesa_sync_start = pipe->stream->timing.v_addressable +
1217 pipe->stream->timing.v_border_bottom +
1218 pipe->stream->timing.v_front_porch;
1220 asic_blank_end = (pipe->stream->timing.v_total -
1222 pipe->stream->timing.v_border_top)
1223 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1226 (pipe->stream->timing.v_border_top +
1227 pipe->stream->timing.v_addressable +
1228 pipe->stream->timing.v_border_bottom)
1229 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1231 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1232 pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1234 if (pipe->plane_state) {
1235 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1237 pipe->plane_state->update_flags.bits.full_update = 1;
1240 ((pipe->stream->view_format ==
1242 pipe->stream->view_format ==
1244 (pipe->stream->timing.timing_3d_format ==
1246 pipe->stream->timing.timing_3d_format ==
1248 if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1249 /* update previously split pipe */
1255 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1256 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1257 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1258 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1260 /* pipe not split previously needs split */
1261 hsplit_pipe = resource_find_free_secondary_pipe_legacy(&context->res_ctx, pool, pipe);
1263 split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1267 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1268 /* merge previously split pipe */
1269 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1271 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1279 resource_build_scaling_params(pipe);
1281 /* for now important to do this after pipe split for building e2e params */
1282 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);