dc/dcn31/dcn31_hpo_dp_link_encoder.h

36 #define DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id) \
37 	SRI(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \
38 	SRI(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \
39 	SRI(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \
40 	SRI(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \
41 	SRI(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \
42 	SRI(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \
43 	SRI(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \
44 	SRI(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \
45 	SRI(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \
46 	SRI(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \
47 	SRI(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \
48 	SRI(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \
49 	SRI(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \
50 	SRI(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \
51 	SRI(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \
52 	SRI(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \
53 	SRI(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \
54 	SRI(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \
55 	SRI(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \
56 	SRI(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \
57 	SRI(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \
58 	SRI(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \
59 	SRI(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \
60 	SRI(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \
61 	SRI(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \
62 	SRI(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \
63 	SRI(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \
64 	SRI(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \
65 	SRI(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id)
67 #define DCN3_1_RDPCSTX_REG_LIST(id) \
68 	SRII(RDPCSTX_PHY_CNTL6, RDPCSTX, id)