Lines Matching refs:type
645 #define MPC_REG_FIELD_LIST_DCN3_0(type) \
646 MPC_REG_FIELD_LIST_DCN2_0(type) \
647 type MPC_DWB0_MUX;\
648 type MPC_DWB0_MUX_STATUS;\
649 type MPC_OUT_RATE_CONTROL;\
650 type MPC_OUT_RATE_CONTROL_DISABLE;\
651 type MPC_OUT_FLOW_CONTROL_MODE;\
652 type MPC_OUT_FLOW_CONTROL_COUNT; \
653 type MPCC_GAMUT_REMAP_MODE; \
654 type MPCC_GAMUT_REMAP_MODE_CURRENT;\
655 type MPCC_GAMUT_REMAP_COEF_FORMAT; \
656 type MPCC_GAMUT_REMAP_C11_A; \
657 type MPCC_GAMUT_REMAP_C12_A; \
658 type MPC_RMU0_MUX; \
659 type MPC_RMU1_MUX; \
660 type MPC_RMU0_MUX_STATUS; \
661 type MPC_RMU1_MUX_STATUS; \
662 type MPC_RMU0_MEM_PWR_FORCE;\
663 type MPC_RMU0_MEM_PWR_DIS;\
664 type MPC_RMU0_MEM_LOW_PWR_MODE;\
665 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\
666 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\
667 type MPC_RMU1_MEM_PWR_FORCE;\
668 type MPC_RMU1_MEM_PWR_DIS;\
669 type MPC_RMU1_MEM_LOW_PWR_MODE;\
670 type MPC_RMU1_SHAPER_MEM_PWR_STATE;\
671 type MPC_RMU1_3DLUT_MEM_PWR_STATE;\
672 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
673 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\
674 type MPCC_OGAM_RAMA_OFFSET_B;\
675 type MPCC_OGAM_RAMA_OFFSET_G;\
676 type MPCC_OGAM_RAMA_OFFSET_R;\
677 type MPCC_OGAM_SELECT; \
678 type MPCC_OGAM_PWL_DISABLE; \
679 type MPCC_OGAM_MODE_CURRENT; \
680 type MPCC_OGAM_SELECT_CURRENT; \
681 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \
682 type MPCC_OGAM_LUT_READ_COLOR_SEL; \
683 type MPCC_OGAM_LUT_READ_DBG; \
684 type MPCC_OGAM_LUT_HOST_SEL; \
685 type MPCC_OGAM_LUT_CONFIG_MODE; \
686 type MPCC_OGAM_LUT_STATUS; \
687 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\
688 type MPCC_OGAM_MEM_LOW_PWR_MODE;\
689 type MPCC_OGAM_MEM_PWR_STATE;\
690 type MPC_RMU_3DLUT_MODE; \
691 type MPC_RMU_3DLUT_SIZE; \
692 type MPC_RMU_3DLUT_MODE_CURRENT; \
693 type MPC_RMU_3DLUT_WRITE_EN_MASK;\
694 type MPC_RMU_3DLUT_RAM_SEL;\
695 type MPC_RMU_3DLUT_30BIT_EN;\
696 type MPC_RMU_3DLUT_CONFIG_STATUS;\
697 type MPC_RMU_3DLUT_READ_SEL;\
698 type MPC_RMU_3DLUT_INDEX;\
699 type MPC_RMU_3DLUT_DATA0;\
700 type MPC_RMU_3DLUT_DATA1;\
701 type MPC_RMU_3DLUT_DATA_30BIT;\
702 type MPC_RMU_SHAPER_LUT_MODE;\
703 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\
704 type MPC_RMU_SHAPER_OFFSET_R;\
705 type MPC_RMU_SHAPER_OFFSET_G;\
706 type MPC_RMU_SHAPER_OFFSET_B;\
707 type MPC_RMU_SHAPER_SCALE_R;\
708 type MPC_RMU_SHAPER_SCALE_G;\
709 type MPC_RMU_SHAPER_SCALE_B;\
710 type MPC_RMU_SHAPER_LUT_INDEX;\
711 type MPC_RMU_SHAPER_LUT_DATA;\
712 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\
713 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\
714 type MPC_RMU_SHAPER_CONFIG_STATUS;\
715 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\
716 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
717 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\
718 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
719 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
720 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
721 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
722 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
723 type MPC_RMU_SHAPER_MODE_CURRENT
725 #define MPC_REG_FIELD_LIST_DCN32(type) \
726 type MPCC_MOVABLE_CM_LOCATION_CNTL;\
727 type MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT;\
728 type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\
729 type MPCC_MCM_SHAPER_MEM_PWR_DIS;\
730 type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\
731 type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\
732 type MPCC_MCM_3DLUT_MEM_PWR_DIS;\
733 type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\
734 type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\
735 type MPCC_MCM_1DLUT_MEM_PWR_DIS;\
736 type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\
737 type MPCC_MCM_SHAPER_MEM_PWR_STATE;\
738 type MPCC_MCM_3DLUT_MEM_PWR_STATE;\
739 type MPCC_MCM_1DLUT_MEM_PWR_STATE;\
740 type MPCC_MCM_3DLUT_MODE; \
741 type MPCC_MCM_3DLUT_SIZE; \
742 type MPCC_MCM_3DLUT_MODE_CURRENT; \
743 type MPCC_MCM_3DLUT_WRITE_EN_MASK;\
744 type MPCC_MCM_3DLUT_RAM_SEL;\
745 type MPCC_MCM_3DLUT_30BIT_EN;\
746 type MPCC_MCM_3DLUT_CONFIG_STATUS;\
747 type MPCC_MCM_3DLUT_READ_SEL;\
748 type MPCC_MCM_3DLUT_INDEX;\
749 type MPCC_MCM_3DLUT_DATA0;\
750 type MPCC_MCM_3DLUT_DATA1;\
751 type MPCC_MCM_3DLUT_DATA_30BIT;\
752 type MPCC_MCM_SHAPER_LUT_MODE;\
753 type MPCC_MCM_SHAPER_MODE_CURRENT;\
754 type MPCC_MCM_SHAPER_OFFSET_R;\
755 type MPCC_MCM_SHAPER_OFFSET_G;\
756 type MPCC_MCM_SHAPER_OFFSET_B;\
757 type MPCC_MCM_SHAPER_SCALE_R;\
758 type MPCC_MCM_SHAPER_SCALE_G;\
759 type MPCC_MCM_SHAPER_SCALE_B;\
760 type MPCC_MCM_SHAPER_LUT_INDEX;\
761 type MPCC_MCM_SHAPER_LUT_DATA;\
762 type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\
763 type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\
764 type MPCC_MCM_SHAPER_CONFIG_STATUS;\
765 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\
766 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
767 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\
768 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
769 type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
770 type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
771 type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
772 type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
773 type MPCC_MCM_1DLUT_MODE;\
774 type MPCC_MCM_1DLUT_SELECT;\
775 type MPCC_MCM_1DLUT_PWL_DISABLE;\
776 type MPCC_MCM_1DLUT_MODE_CURRENT;\
777 type MPCC_MCM_1DLUT_SELECT_CURRENT;\
778 type MPCC_MCM_1DLUT_LUT_INDEX;\
779 type MPCC_MCM_1DLUT_LUT_DATA;\
780 type MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK;\
781 type MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL;\
782 type MPCC_MCM_1DLUT_LUT_HOST_SEL;\
783 type MPCC_MCM_1DLUT_LUT_CONFIG_MODE;\
784 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;\
785 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B;\
786 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B;\
787 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B;\
788 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B;\
789 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B;\
790 type MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B;\
791 type MPCC_MCM_1DLUT_RAMA_OFFSET_B;\
792 type MPCC_MCM_1DLUT_RAMA_OFFSET_G;\
793 type MPCC_MCM_1DLUT_RAMA_OFFSET_R;\
794 type MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET;\
795 type MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS;\
796 type MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET;\
797 type MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS
903 #define MPC_REG_FIELD_LIST_DCN3_03(type) \
904 MPC_REG_FIELD_LIST_DCN2_0(type) \
905 type MPC_DWB0_MUX;\
906 type MPC_DWB0_MUX_STATUS;\
907 type MPC_OUT_RATE_CONTROL;\
908 type MPC_OUT_RATE_CONTROL_DISABLE;\
909 type MPC_OUT_FLOW_CONTROL_MODE;\
910 type MPC_OUT_FLOW_CONTROL_COUNT; \
911 type MPCC_GAMUT_REMAP_MODE; \
912 type MPCC_GAMUT_REMAP_MODE_CURRENT;\
913 type MPCC_GAMUT_REMAP_COEF_FORMAT; \
914 type MPCC_GAMUT_REMAP_C11_A; \
915 type MPCC_GAMUT_REMAP_C12_A; \
916 type MPC_RMU0_MUX; \
917 type MPC_RMU0_MUX_STATUS; \
918 type MPC_RMU0_MEM_PWR_FORCE;\
919 type MPC_RMU0_MEM_PWR_DIS;\
920 type MPC_RMU0_MEM_LOW_PWR_MODE;\
921 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\
922 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\
923 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \
924 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\
925 type MPCC_OGAM_RAMA_OFFSET_B;\
926 type MPCC_OGAM_RAMA_OFFSET_G;\
927 type MPCC_OGAM_RAMA_OFFSET_R;\
928 type MPCC_OGAM_SELECT; \
929 type MPCC_OGAM_PWL_DISABLE; \
930 type MPCC_OGAM_MODE_CURRENT; \
931 type MPCC_OGAM_SELECT_CURRENT; \
932 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \
933 type MPCC_OGAM_LUT_READ_COLOR_SEL; \
934 type MPCC_OGAM_LUT_READ_DBG; \
935 type MPCC_OGAM_LUT_HOST_SEL; \
936 type MPCC_OGAM_LUT_CONFIG_MODE; \
937 type MPCC_OGAM_LUT_STATUS; \
938 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\
939 type MPCC_OGAM_MEM_LOW_PWR_MODE;\
940 type MPCC_OGAM_MEM_PWR_STATE;\
941 type MPC_RMU_3DLUT_MODE; \
942 type MPC_RMU_3DLUT_SIZE; \
943 type MPC_RMU_3DLUT_MODE_CURRENT; \
944 type MPC_RMU_3DLUT_WRITE_EN_MASK;\
945 type MPC_RMU_3DLUT_RAM_SEL;\
946 type MPC_RMU_3DLUT_30BIT_EN;\
947 type MPC_RMU_3DLUT_CONFIG_STATUS;\
948 type MPC_RMU_3DLUT_READ_SEL;\
949 type MPC_RMU_3DLUT_INDEX;\
950 type MPC_RMU_3DLUT_DATA0;\
951 type MPC_RMU_3DLUT_DATA1;\
952 type MPC_RMU_3DLUT_DATA_30BIT;\
953 type MPC_RMU_SHAPER_LUT_MODE;\
954 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\
955 type MPC_RMU_SHAPER_OFFSET_R;\
956 type MPC_RMU_SHAPER_OFFSET_G;\
957 type MPC_RMU_SHAPER_OFFSET_B;\
958 type MPC_RMU_SHAPER_SCALE_R;\
959 type MPC_RMU_SHAPER_SCALE_G;\
960 type MPC_RMU_SHAPER_SCALE_B;\
961 type MPC_RMU_SHAPER_LUT_INDEX;\
962 type MPC_RMU_SHAPER_LUT_DATA;\
963 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\
964 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\
965 type MPC_RMU_SHAPER_CONFIG_STATUS;\
966 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\
967 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\
968 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\
969 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\
970 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\
971 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\
972 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\
973 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\
974 type MPC_RMU_SHAPER_MODE_CURRENT