Lines Matching refs:type
116 #define DCCG_REG_FIELD_LIST(type) \
117 type DPPCLK0_DTO_PHASE;\
118 type DPPCLK0_DTO_MODULO;\
119 type DPPCLK_DTO_ENABLE[6];\
120 type DPPCLK_DTO_DB_EN[6];\
121 type REFCLK_CLOCK_EN;\
122 type REFCLK_SRC_SEL;\
123 type DISPCLK_STEP_DELAY;\
124 type DISPCLK_STEP_SIZE;\
125 type DISPCLK_FREQ_RAMP_DONE;\
126 type DISPCLK_MAX_ERRDET_CYCLES;\
127 type DCCG_FIFO_ERRDET_RESET;\
128 type DCCG_FIFO_ERRDET_STATE;\
129 type DCCG_FIFO_ERRDET_OVR_EN;\
130 type DISPCLK_CHG_FWD_CORR_DISABLE;\
131 type DISPCLK_FREQ_CHANGE_CNTL;\
132 type OTG_ADD_PIXEL[MAX_PIPES];\
133 type OTG_DROP_PIXEL[MAX_PIPES];
135 #define DCCG3_REG_FIELD_LIST(type) \
136 type HDMICHARCLK0_EN;\
137 type HDMICHARCLK0_SRC_SEL;\
138 type PHYASYMCLK_FORCE_EN;\
139 type PHYASYMCLK_FORCE_SRC_SEL;\
140 type PHYBSYMCLK_FORCE_EN;\
141 type PHYBSYMCLK_FORCE_SRC_SEL;\
142 type PHYCSYMCLK_FORCE_EN;\
143 type PHYCSYMCLK_FORCE_SRC_SEL;
145 #define DCCG31_REG_FIELD_LIST(type) \
146 type PHYDSYMCLK_FORCE_EN;\
147 type PHYDSYMCLK_FORCE_SRC_SEL;\
148 type PHYESYMCLK_FORCE_EN;\
149 type PHYESYMCLK_FORCE_SRC_SEL;\
150 type DPSTREAMCLK_PIPE0_EN;\
151 type DPSTREAMCLK_PIPE1_EN;\
152 type DPSTREAMCLK_PIPE2_EN;\
153 type DPSTREAMCLK_PIPE3_EN;\
154 type HDMISTREAMCLK0_SRC_SEL;\
155 type HDMISTREAMCLK0_DTO_FORCE_DIS;\
156 type SYMCLK32_SE0_SRC_SEL;\
157 type SYMCLK32_SE1_SRC_SEL;\
158 type SYMCLK32_SE2_SRC_SEL;\
159 type SYMCLK32_SE3_SRC_SEL;\
160 type SYMCLK32_SE0_EN;\
161 type SYMCLK32_SE1_EN;\
162 type SYMCLK32_SE2_EN;\
163 type SYMCLK32_SE3_EN;\
164 type SYMCLK32_LE0_SRC_SEL;\
165 type SYMCLK32_LE1_SRC_SEL;\
166 type SYMCLK32_LE0_EN;\
167 type SYMCLK32_LE1_EN;\
168 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
169 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
170 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
171 type DTBCLK_DTO_DIV[MAX_PIPES];\
172 type DCCG_AUDIO_DTO_SEL;\
173 type DCCG_AUDIO_DTO0_SOURCE_SEL;\
174 type DENTIST_DISPCLK_CHG_MODE;\
175 type DSCCLK0_DTO_PHASE;\
176 type DSCCLK0_DTO_MODULO;\
177 type DSCCLK1_DTO_PHASE;\
178 type DSCCLK1_DTO_MODULO;\
179 type DSCCLK2_DTO_PHASE;\
180 type DSCCLK2_DTO_MODULO;\
181 type DSCCLK0_DTO_ENABLE;\
182 type DSCCLK1_DTO_ENABLE;\
183 type DSCCLK2_DTO_ENABLE;\
184 type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
185 type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
186 type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
187 type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
188 type SYMCLK32_SE0_GATE_DISABLE;\
189 type SYMCLK32_SE1_GATE_DISABLE;\
190 type SYMCLK32_SE2_GATE_DISABLE;\
191 type SYMCLK32_SE3_GATE_DISABLE;\
192 type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
193 type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
194 type SYMCLK32_LE0_GATE_DISABLE;\
195 type SYMCLK32_LE1_GATE_DISABLE;\
196 type DPSTREAMCLK_ROOT_GATE_DISABLE;\
197 type DPSTREAMCLK_GATE_DISABLE;\
198 type HDMISTREAMCLK0_DTO_PHASE;\
199 type HDMISTREAMCLK0_DTO_MODULO;\
200 type HDMICHARCLK0_GATE_DISABLE;\
201 type HDMICHARCLK0_ROOT_GATE_DISABLE; \
202 type PHYASYMCLK_GATE_DISABLE; \
203 type PHYBSYMCLK_GATE_DISABLE; \
204 type PHYCSYMCLK_GATE_DISABLE; \
205 type PHYDSYMCLK_GATE_DISABLE; \
206 type PHYESYMCLK_GATE_DISABLE;
208 #define DCCG314_REG_FIELD_LIST(type) \
209 type DSCCLK3_DTO_PHASE;\
210 type DSCCLK3_DTO_MODULO;\
211 type DSCCLK3_DTO_ENABLE;\
212 type DENTIST_DISPCLK_RDIVIDER;\
213 type DENTIST_DISPCLK_WDIVIDER;
215 #define DCCG32_REG_FIELD_LIST(type) \
216 type DPSTREAMCLK0_EN;\
217 type DPSTREAMCLK1_EN;\
218 type DPSTREAMCLK2_EN;\
219 type DPSTREAMCLK3_EN;\
220 type DPSTREAMCLK0_SRC_SEL;\
221 type DPSTREAMCLK1_SRC_SEL;\
222 type DPSTREAMCLK2_SRC_SEL;\
223 type DPSTREAMCLK3_SRC_SEL;\
224 type HDMISTREAMCLK0_EN;\
225 type OTG0_PIXEL_RATE_DIVK1;\
226 type OTG0_PIXEL_RATE_DIVK2;\
227 type OTG1_PIXEL_RATE_DIVK1;\
228 type OTG1_PIXEL_RATE_DIVK2;\
229 type OTG2_PIXEL_RATE_DIVK1;\
230 type OTG2_PIXEL_RATE_DIVK2;\
231 type OTG3_PIXEL_RATE_DIVK1;\
232 type OTG3_PIXEL_RATE_DIVK2;\
233 type DTBCLK_P0_SRC_SEL;\
234 type DTBCLK_P0_EN;\
235 type DTBCLK_P1_SRC_SEL;\
236 type DTBCLK_P1_EN;\
237 type DTBCLK_P2_SRC_SEL;\
238 type DTBCLK_P2_EN;\
239 type DTBCLK_P3_SRC_SEL;\
240 type DTBCLK_P3_EN;\
241 type DENTIST_DISPCLK_CHG_DONE;
243 #define DCCG35_REG_FIELD_LIST(type) \
244 type DPPCLK0_EN;\
245 type DPPCLK1_EN;\
246 type DPPCLK2_EN;\
247 type DPPCLK3_EN;\
248 type DSCCLK0_EN;\
249 type DSCCLK1_EN;\
250 type DSCCLK2_EN;\
251 type DSCCLK3_EN;\
252 type DISPCLK_DCCG_GATE_DISABLE;\
253 type DCCG_GLOBAL_FGCG_REP_DIS; \
254 type PHYASYMCLK_EN;\
255 type PHYASYMCLK_SRC_SEL;\
256 type PHYBSYMCLK_EN;\
257 type PHYBSYMCLK_SRC_SEL;\
258 type PHYCSYMCLK_EN;\
259 type PHYCSYMCLK_SRC_SEL;\
260 type PHYDSYMCLK_EN;\
261 type PHYDSYMCLK_SRC_SEL;\
262 type PHYESYMCLK_EN;\
263 type PHYESYMCLK_SRC_SEL;\
264 type PHYASYMCLK_ROOT_GATE_DISABLE;\
265 type PHYBSYMCLK_ROOT_GATE_DISABLE;\
266 type PHYCSYMCLK_ROOT_GATE_DISABLE;\
267 type PHYDSYMCLK_ROOT_GATE_DISABLE;\
268 type PHYESYMCLK_ROOT_GATE_DISABLE;\
269 type HDMISTREAMCLK0_GATE_DISABLE;\
270 type HDMISTREAMCLK1_GATE_DISABLE;\
271 type HDMISTREAMCLK2_GATE_DISABLE;\
272 type HDMISTREAMCLK3_GATE_DISABLE;\
273 type HDMISTREAMCLK4_GATE_DISABLE;\
274 type HDMISTREAMCLK5_GATE_DISABLE;\
275 type SYMCLKA_CLOCK_ENABLE;\
276 type SYMCLKB_CLOCK_ENABLE;\
277 type SYMCLKC_CLOCK_ENABLE;\
278 type SYMCLKD_CLOCK_ENABLE;\
279 type SYMCLKE_CLOCK_ENABLE;\
280 type SYMCLKA_FE_EN;\
281 type SYMCLKB_FE_EN;\
282 type SYMCLKC_FE_EN;\
283 type SYMCLKD_FE_EN;\
284 type SYMCLKE_FE_EN;\
285 type SYMCLKA_SRC_SEL;\
286 type SYMCLKB_SRC_SEL;\
287 type SYMCLKC_SRC_SEL;\
288 type SYMCLKD_SRC_SEL;\
289 type SYMCLKE_SRC_SEL;\
290 type SYMCLKA_FE_SRC_SEL;\
291 type SYMCLKB_FE_SRC_SEL;\
292 type SYMCLKC_FE_SRC_SEL;\
293 type SYMCLKD_FE_SRC_SEL;\
294 type SYMCLKE_FE_SRC_SEL;\
295 type DTBCLK_P0_GATE_DISABLE;\
296 type DTBCLK_P1_GATE_DISABLE;\
297 type DTBCLK_P2_GATE_DISABLE;\
298 type DTBCLK_P3_GATE_DISABLE;\
299 type DSCCLK0_ROOT_GATE_DISABLE;\
300 type DSCCLK1_ROOT_GATE_DISABLE;\
301 type DSCCLK2_ROOT_GATE_DISABLE;\
302 type DSCCLK3_ROOT_GATE_DISABLE;\
303 type SYMCLKA_FE_ROOT_GATE_DISABLE;\
304 type SYMCLKB_FE_ROOT_GATE_DISABLE;\
305 type SYMCLKC_FE_ROOT_GATE_DISABLE;\
306 type SYMCLKD_FE_ROOT_GATE_DISABLE;\
307 type SYMCLKE_FE_ROOT_GATE_DISABLE;\
308 type DPPCLK0_ROOT_GATE_DISABLE;\
309 type DPPCLK1_ROOT_GATE_DISABLE;\
310 type DPPCLK2_ROOT_GATE_DISABLE;\
311 type DPPCLK3_ROOT_GATE_DISABLE;\
312 type HDMISTREAMCLK0_ROOT_GATE_DISABLE;\
313 type SYMCLKA_ROOT_GATE_DISABLE;\
314 type SYMCLKB_ROOT_GATE_DISABLE;\
315 type SYMCLKC_ROOT_GATE_DISABLE;\
316 type SYMCLKD_ROOT_GATE_DISABLE;\
317 type SYMCLKE_ROOT_GATE_DISABLE;\
318 type PHYA_REFCLK_ROOT_GATE_DISABLE;\
319 type PHYB_REFCLK_ROOT_GATE_DISABLE;\
320 type PHYC_REFCLK_ROOT_GATE_DISABLE;\
321 type PHYD_REFCLK_ROOT_GATE_DISABLE;\
322 type PHYE_REFCLK_ROOT_GATE_DISABLE;\
323 type DPSTREAMCLK0_ROOT_GATE_DISABLE;\
324 type DPSTREAMCLK1_ROOT_GATE_DISABLE;\
325 type DPSTREAMCLK2_ROOT_GATE_DISABLE;\
326 type DPSTREAMCLK3_ROOT_GATE_DISABLE;\
327 type DPSTREAMCLK0_GATE_DISABLE;\
328 type DPSTREAMCLK1_GATE_DISABLE;\
329 type DPSTREAMCLK2_GATE_DISABLE;\
330 type DPSTREAMCLK3_GATE_DISABLE;\