dc/dce60/dce60_resource.c

539 					ctx->dc->caps.extended_aux_timeout_support);
867 	struct dc *dc,
874 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
912 		struct dc *dc,
943 	struct dc *dc,
947 	struct dc_context *ctx = dc->ctx;
962 	dc->caps.max_downscale_ratio = 200;
963 	dc->caps.i2c_speed_in_khz = 40;
964 	dc->caps.max_cursor_size = 64;
965 	dc->caps.dual_link_dvi = true;
966 	dc->caps.extended_aux_timeout_support = false;
1029 		init_data.ctx = dc->ctx;
1097 	dc->caps.max_planes =  pool->base.pipe_count;
1099 	for (i = 0; i < dc->caps.max_planes; ++i)
1100 		dc->caps.planes[i] = plane_cap;
1102 	dc->caps.disable_dp_clk_share = true;
1104 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1109 	dce60_hw_sequencer_construct(dc);
1120 	struct dc *dc)
1128 	if (dce60_construct(num_virtual_links, dc, pool))
1138 	struct dc *dc,
1142 	struct dc_context *ctx = dc->ctx;
1157 	dc->caps.max_downscale_ratio = 200;
1158 	dc->caps.i2c_speed_in_khz = 40;
1159 	dc->caps.max_cursor_size = 64;
1160 	dc->caps.is_apu = true;
1227 		init_data.ctx = dc->ctx;
1295 	dc->caps.max_planes =  pool->base.pipe_count;
1297 	for (i = 0; i < dc->caps.max_planes; ++i)
1298 		dc->caps.planes[i] = plane_cap;
1300 	dc->caps.disable_dp_clk_share = true;
1302 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1307 	dce60_hw_sequencer_construct(dc);
1318 	struct dc *dc)
1326 	if (dce61_construct(num_virtual_links, dc, pool))
1336 	struct dc *dc,
1340 	struct dc_context *ctx = dc->ctx;
1355 	dc->caps.max_downscale_ratio = 200;
1356 	dc->caps.i2c_speed_in_khz = 40;
1357 	dc->caps.max_cursor_size = 64;
1358 	dc->caps.is_apu = true;
1421 		init_data.ctx = dc->ctx;
1489 	dc->caps.max_planes =  pool->base.pipe_count;
1491 	for (i = 0; i < dc->caps.max_planes; ++i)
1492 		dc->caps.planes[i] = plane_cap;
1494 	dc->caps.disable_dp_clk_share = true;
1496 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1501 	dce60_hw_sequencer_construct(dc);
1512 	struct dc *dc)
1520 	if (dce64_construct(num_virtual_links, dc, pool))