dc/dce60/dce60_hw_sequencer.c

55 	struct pipe_ctx *pipe_ctx = NULL;
71 		if (res_ctx->pipe_ctx[i].stream) {
73 			pipe_ctx = &res_ctx->pipe_ctx[i];
75 			if (!pipe_ctx)
79 			if (pipe_ctx->pipe_idx != underlay_idx) {
89 	if (!pipe_ctx->stream->link)
93 	if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
97 	if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
101 	if (!pipe_ctx->plane_state)
105 	if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
124 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
126 		params.source_view_width = pipe_ctx->stream->timing.h_addressable;
127 		params.source_view_height = pipe_ctx->stream->timing.v_addressable;
128 		params.inst = pipe_ctx->stream_res.tg->inst;
143 static void dce60_set_default_colors(struct pipe_ctx *pipe_ctx)
148 	default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
149 	default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
151 	default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
155 		pipe_ctx->stream->timing.display_color_depth;
158 	default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
160 	pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
161 					pipe_ctx->plane_res.xfm, &default_adjust);
182 		struct pipe_ctx *pipe_ctx)
188 	if (!pipe_ctx->plane_state->visible)
192 	pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
197 static void dce60_get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
200 	uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
202 	switch (pipe_ctx->plane_res.scl_data.format) {
233 		const struct pipe_ctx *pipe_ctx)
240 		dce60_get_surface_visual_confirm_color(pipe_ctx, &color);
243 				pipe_ctx->stream->output_color_space,
246 	pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
247 		pipe_ctx->plane_res.xfm,
248 		pipe_ctx->plane_res.scl_data.lb_params.depth,
249 		&pipe_ctx->stream->bit_depth_params);
251 	if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
257 		if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
260 		pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
261 				pipe_ctx->stream_res.tg,
265 	pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
266 		&pipe_ctx->plane_res.scl_data);
271 		struct dc *dc, struct pipe_ctx *pipe_ctx)
273 	struct mem_input *mi = pipe_ctx->plane_res.mi;
274 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
288 	dce60_set_default_colors(pipe_ctx);
289 	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
292 			pipe_ctx->stream->output_color_space;
296 			pipe_ctx->stream->csc_color_matrix.matrix[i];
298 		pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
299 				(pipe_ctx->plane_res.xfm, &tbl_entry);
302 	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
307 				pipe_ctx->stream->gamut_remap_matrix.matrix[i];
310 	pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
312 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
314 	dce60_program_scaler(dc, pipe_ctx);
325 		mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
329 				pipe_ctx->plane_res.mi,
335 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
336 			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
337 			pipe_ctx->plane_state->update_flags.bits.gamma_change)
338 		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
340 	if (pipe_ctx->plane_state->update_flags.bits.full_update)
341 		hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
349 			pipe_ctx->pipe_idx,
350 			(void *) pipe_ctx->plane_state,
351 			pipe_ctx->plane_state->address.grph.addr.high_part,
352 			pipe_ctx->plane_state->address.grph.addr.low_part,
353 			pipe_ctx->plane_state->src_rect.x,
354 			pipe_ctx->plane_state->src_rect.y,
355 			pipe_ctx->plane_state->src_rect.width,
356 			pipe_ctx->plane_state->src_rect.height,
357 			pipe_ctx->plane_state->dst_rect.x,
358 			pipe_ctx->plane_state->dst_rect.y,
359 			pipe_ctx->plane_state->dst_rect.width,
360 			pipe_ctx->plane_state->dst_rect.height,
361 			pipe_ctx->plane_state->clip_rect.x,
362 			pipe_ctx->plane_state->clip_rect.y,
363 			pipe_ctx->plane_state->clip_rect.width,
364 			pipe_ctx->plane_state->clip_rect.height);
370 			pipe_ctx->pipe_idx,
371 			pipe_ctx->plane_res.scl_data.viewport.width,
372 			pipe_ctx->plane_res.scl_data.viewport.height,
373 			pipe_ctx->plane_res.scl_data.viewport.x,
374 			pipe_ctx->plane_res.scl_data.viewport.y,
375 			pipe_ctx->plane_res.scl_data.recout.width,
376 			pipe_ctx->plane_res.scl_data.recout.height,
377 			pipe_ctx->plane_res.scl_data.recout.x,
378 			pipe_ctx->plane_res.scl_data.recout.y);
396 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
398 		if (pipe_ctx->stream != stream)
402 		pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
403 				pipe_ctx->plane_res.mi,
404 				pipe_ctx->stream->timing.h_total,
405 				pipe_ctx->stream->timing.v_total,
406 				pipe_ctx->stream->timing.pix_clk_100hz / 10,
409 		dce60_program_front_end_for_pipe(dc, pipe_ctx);
411 		dc->hwss.update_plane_addr(dc, pipe_ctx);
413 		dce60_program_surface_visibility(dc, pipe_ctx);