dc/dce120/dce120_timing_generator.c

43 		generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 		generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
93 					tg110->offsets.crtc);
176 				tg110->offsets.crtc);
192 				tg110->offsets.crtc);
203 				tg110->offsets.crtc);
253 							tg110->offsets.crtc);
261 	dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);
315 									tg110->offsets.crtc);
377 			tg110->offsets.crtc);
516 			tg110->offsets.crtc);
521 			tg110->offsets.crtc,
531 		tg110->offsets.crtc,
605 			tg110->offsets.crtc);
633 				tg110->offsets.crtc);
655 			tg110->offsets.crtc,
674 				tg110->offsets.crtc);
678 		tg110->offsets.crtc,
715 			tg110->offsets.crtc);
743 			tg110->offsets.crtc, 0);
903 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);
942 			dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
955 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
1029 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0);
1032 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);
1044 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc,  value);
1045 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);
1046 		dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value);
1086 				  tg110->offsets.crtc);
1104 			   tg110->offsets.crtc, 0);
1146 				  tg110->offsets.crtc);
1154 				  tg110->offsets.crtc);
1159 				  tg110->offsets.crtc);
1207 	const struct dce110_timing_generator_offsets *offsets)
1212 	tg110->offsets = *offsets;