dc/dce/dce_transform.h

38 #define XFM_COMMON_REG_LIST_DCE_BASE(id) \
39 	SRI(LB_DATA_FORMAT, LB, id), \
40 	SRI(GAMUT_REMAP_CONTROL, DCP, id), \
41 	SRI(GAMUT_REMAP_C11_C12, DCP, id), \
42 	SRI(GAMUT_REMAP_C13_C14, DCP, id), \
43 	SRI(GAMUT_REMAP_C21_C22, DCP, id), \
44 	SRI(GAMUT_REMAP_C23_C24, DCP, id), \
45 	SRI(GAMUT_REMAP_C31_C32, DCP, id), \
46 	SRI(GAMUT_REMAP_C33_C34, DCP, id), \
47 	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
48 	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
49 	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
50 	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
51 	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
52 	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
53 	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
54 	SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
55 	SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
56 	SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
57 	SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
58 	SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
59 	SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
60 	SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
61 	SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
62 	SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
63 	SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
64 	SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
65 	SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
66 	SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
67 	SRI(REGAMMA_LUT_INDEX, DCP, id), \
68 	SRI(REGAMMA_LUT_DATA, DCP, id), \
69 	SRI(REGAMMA_CONTROL, DCP, id), \
70 	SRI(DENORM_CONTROL, DCP, id), \
71 	SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
72 	SRI(OUT_ROUND_CONTROL, DCP, id), \
73 	SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
74 	SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
75 	SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
76 	SRI(SCL_MODE, SCL, id), \
77 	SRI(SCL_TAP_CONTROL, SCL, id), \
78 	SRI(SCL_CONTROL, SCL, id), \
79 	SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 	SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 	SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 	SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 	SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 	SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
86 	SRI(VIEWPORT_START, SCL, id), \
87 	SRI(VIEWPORT_SIZE, SCL, id), \
88 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
89 	SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
90 	SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
91 	SRI(SCL_VERT_FILTER_INIT, SCL, id), \
92 	SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
93 	SRI(LB_MEMORY_CTRL, LB, id), \
94 	SRI(SCL_UPDATE, SCL, id), \
95 	SRI(SCL_F_SHARP_CONTROL, SCL, id)
97 #define XFM_COMMON_REG_LIST_DCE80(id) \
98 	XFM_COMMON_REG_LIST_DCE_BASE(id), \
99 	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
101 #define XFM_COMMON_REG_LIST_DCE100(id) \
102 	XFM_COMMON_REG_LIST_DCE_BASE(id), \
103 	SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 	SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
106 #define XFM_COMMON_REG_LIST_DCE110(id) \
107 	XFM_COMMON_REG_LIST_DCE_BASE(id), \
108 	SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
109 	SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
112 #define XFM_COMMON_REG_LIST_DCE60_BASE(id) \
113 	SRI(DATA_FORMAT, LB, id), \
114 	SRI(GAMUT_REMAP_CONTROL, DCP, id), \
115 	SRI(GAMUT_REMAP_C11_C12, DCP, id), \
116 	SRI(GAMUT_REMAP_C13_C14, DCP, id), \
117 	SRI(GAMUT_REMAP_C21_C22, DCP, id), \
118 	SRI(GAMUT_REMAP_C23_C24, DCP, id), \
119 	SRI(GAMUT_REMAP_C31_C32, DCP, id), \
120 	SRI(GAMUT_REMAP_C33_C34, DCP, id), \
121 	SRI(OUTPUT_CSC_C11_C12, DCP, id), \
122 	SRI(OUTPUT_CSC_C13_C14, DCP, id), \
123 	SRI(OUTPUT_CSC_C21_C22, DCP, id), \
124 	SRI(OUTPUT_CSC_C23_C24, DCP, id), \
125 	SRI(OUTPUT_CSC_C31_C32, DCP, id), \
126 	SRI(OUTPUT_CSC_C33_C34, DCP, id), \
127 	SRI(OUTPUT_CSC_CONTROL, DCP, id), \
128 	SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
129 	SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
130 	SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
131 	SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
132 	SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
133 	SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
134 	SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
135 	SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
136 	SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
137 	SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
138 	SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
139 	SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
140 	SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
141 	SRI(REGAMMA_LUT_INDEX, DCP, id), \
142 	SRI(REGAMMA_LUT_DATA, DCP, id), \
143 	SRI(REGAMMA_CONTROL, DCP, id), \
144 	SRI(DENORM_CONTROL, DCP, id), \
145 	SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
146 	SRI(OUT_ROUND_CONTROL, DCP, id), \
147 	SRI(SCL_TAP_CONTROL, SCL, id), \
148 	SRI(SCL_CONTROL, SCL, id), \
149 	SRI(SCL_BYPASS_CONTROL, SCL, id), \
150 	SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
151 	SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
152 	SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
153 	SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
154 	SRI(SCL_COEF_RAM_SELECT, SCL, id), \
155 	SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
156 	SRI(VIEWPORT_START, SCL, id), \
157 	SRI(VIEWPORT_SIZE, SCL, id), \
158 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
159 	SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
160 	SRI(SCL_VERT_FILTER_INIT, SCL, id), \
161 	SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
162 	SRI(DC_LB_MEMORY_SPLIT, LB, id), \
163 	SRI(DC_LB_MEM_SIZE, LB, id), \
164 	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
165 	SRI(SCL_UPDATE, SCL, id), \
166 	SRI(SCL_F_SHARP_CONTROL, SCL, id)
168 #define XFM_COMMON_REG_LIST_DCE60(id) \
169 	XFM_COMMON_REG_LIST_DCE60_BASE(id), \
170 	SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)