dc/core/dc_hw_sequencer.c

560 		struct block_sequence block_sequence[],
579 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
580 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
581 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
583 		block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
587 		block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
588 		block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
589 		block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
590 		block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
595 		block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
596 		block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
597 		block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
598 		block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
607 				block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
608 				block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
609 				block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
613 				block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
614 				block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
615 				block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
616 				block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
622 					block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
623 					block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &current_mpc_pipe->plane_state->address;
624 					block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
625 					block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
629 				block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
630 				block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
631 				block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
636 				block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
637 				block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
638 				block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
639 				block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
644 				block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
645 				block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
649 				block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
650 				block_sequence[*num_steps].func = DPP_SETUP_DPP;
654 				block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
655 				block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
659 				block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
660 				block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
661 				block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
662 				block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
667 				block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
668 				block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
669 				block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
670 				block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
674 					block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
675 					block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
676 					block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
677 					block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
678 					block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
681 					block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
682 					block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
683 					block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
684 					block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
685 					block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
695 		block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
696 		block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
697 		block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
698 		block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
702 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
703 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
704 		block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
706 		block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
719 				block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
720 				block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
730 		struct block_sequence block_sequence[],
738 		params = &(block_sequence[i].params);
739 		switch (block_sequence[i].func) {