clk_mgr/dcn35/dcn35_clk_mgr.c

469 	.entries = {
506 	.entries = {
575 		/* skip empty entries, the smu array has no holes*/
576 		if (!bw_params->wm_table.entries[i].valid)
579 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
580 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
591 						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
594 					bw_params->clk_table.entries[i].dcfclk_mhz;
711 	struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
754 		/* Invalid number of entries in the table from PMFW. */
772 			if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
775 		bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
776 		bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
777 		bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
780 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
781 		bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
782 		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
783 		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
784 		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
785 		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
786 		bw_params->clk_table.entries[i].wck_ratio =
790 		bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
798 		bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
799 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
800 		bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
801 		bw_params->clk_table.entries[i].dcfclk_mhz =
803 		bw_params->clk_table.entries[i].socclk_mhz =
805 		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
806 		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
807 		bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
814 	bw_params->clk_table.entries[i].socclk_mhz =
816 	bw_params->clk_table.entries[i].dispclk_mhz =
818 	bw_params->clk_table.entries[i].dppclk_mhz =
820 	bw_params->clk_table.entries[i].fclk_mhz =
823 	bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
824 	bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
825 	bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
838 		if (!bw_params->clk_table.entries[i].fclk_mhz) {
839 			bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
840 			bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
841 			bw_params->clk_table.entries[i].voltage = def_max.voltage;
843 		if (!bw_params->clk_table.entries[i].dcfclk_mhz)
844 			bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
845 		if (!bw_params->clk_table.entries[i].socclk_mhz)
846 			bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
847 		if (!bw_params->clk_table.entries[i].dispclk_mhz)
848 			bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
849 		if (!bw_params->clk_table.entries[i].dppclk_mhz)
850 			bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
851 		if (!bw_params->clk_table.entries[i].fclk_mhz)
852 			bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
853 		if (!bw_params->clk_table.entries[i].phyclk_mhz)
854 			bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
855 		if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
856 			bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
857 		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
858 			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
860 	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
866 		bw_params->wm_table.entries[i].wm_inst = i;
869 			bw_params->wm_table.entries[i].valid = false;
873 		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
874 		bw_params->wm_table.entries[i].valid = true;