Lines Matching refs:clk_table
337 .clk_table = {
444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
447 bw_params->clk_table.entries[i].dcfclk_mhz;
583 bw_params->clk_table.num_entries = j + 1;
594 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
595 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
596 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
597 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
600 bw_params->clk_table.entries[i].wck_ratio = 2;
603 bw_params->clk_table.entries[i].wck_ratio = 4;
606 bw_params->clk_table.entries[i].wck_ratio = 1;
608 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
609 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
610 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
611 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
622 if (i >= bw_params->clk_table.num_entries) {