Lines Matching refs:clk_table
409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
412 bw_params->clk_table.entries[i].dcfclk_mhz;
493 .clk_table = {
587 bw_params->clk_table.num_entries = j + 1;
589 for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) {
590 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
591 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
592 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
593 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
595 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
596 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
597 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
598 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCFCLK_DPM_LEVELS);
606 if (i >= bw_params->clk_table.num_entries) {