Lines Matching defs:pp_smu
195 struct pp_smu_funcs_rv *pp_smu = NULL;
202 ASSERT(clk_mgr->pp_smu);
207 pp_smu = &clk_mgr->pp_smu->rv_funcs;
220 if (pp_smu->set_display_count)
221 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
261 if (pp_smu->set_hard_min_fclk_by_freq &&
262 pp_smu->set_hard_min_dcfclk_by_freq &&
263 pp_smu->set_min_deep_sleep_dcfclk) {
264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));
266 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));
281 if (pp_smu->set_hard_min_fclk_by_freq &&
282 pp_smu->set_hard_min_dcfclk_by_freq &&
283 pp_smu->set_min_deep_sleep_dcfclk) {
284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));
285 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));
286 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));
294 struct pp_smu_funcs_rv *pp_smu = NULL;
296 if (clk_mgr->pp_smu) {
297 pp_smu = &clk_mgr->pp_smu->rv_funcs;
299 if (pp_smu->set_pme_wa_enable)
300 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
316 void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)
322 clk_mgr->pp_smu = pp_smu;