clk_mgr/dce110/dce110_clk_mgr.c

92 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
97 	for (j = 0; j < context->stream_count; j++) {
98 		struct dc_stream_state *stream = context->streams[j];
120 	const struct dc_state *context,
126 	for (j = 0; j < context->stream_count; j++) {
129 		const struct dc_stream_state *stream = context->streams[j];
135 			if (stream == context->res_ctx.pipe_ctx[k].stream) {
136 				pipe_ctx = &context->res_ctx.pipe_ctx[k];
174 	struct dc_state *context)
176 	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
183 		context->bw_ctx.bw.dce.all_displays_in_sync;
185 			context->bw_ctx.bw.dce.nbp_state_change_enable == false;
187 			context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
189 			context->bw_ctx.bw.dce.cpup_state_change_enable == false;
191 			context->bw_ctx.bw.dce.blackout_recovery_time_us;
199 	     ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
205 		pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
211 			context->bw_ctx.bw.dce.sclk_khz);
220 	pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
224 			= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
227 						dce110_get_min_vblank_time_us(context);
233 	dce110_fill_display_configs(context, pp_display_cfg);
238 			&context->streams[0]->timing;
250 			struct dc_state *context,
255 	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
261 	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
270 		context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk);
273 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);