Lines Matching refs:context
162 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
165 uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context)
171 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
196 struct dc_state *context)
201 int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);
208 if (context->bw_ctx.bw.dce.dispclk_khz >
218 < context->bw_ctx.bw.dce.dispclk_khz)
385 struct dc_state *context)
387 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
389 pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
391 dce110_fill_display_configs(context, pp_display_cfg);
398 struct dc_state *context,
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
409 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
421 dce_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);