dc/bios/command_table.c

940 	struct bp_pixel_clock_parameters *bp_params);
943 	struct bp_pixel_clock_parameters *bp_params);
946 	struct bp_pixel_clock_parameters *bp_params);
949 	struct bp_pixel_clock_parameters *bp_params);
976 	struct bp_pixel_clock_parameters *bp_params)
984 	if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
986 	else if (CLOCK_SOURCE_ID_PLL2 == bp_params->pll_id)
992 			cpu_to_le16((uint16_t)bp_params->reference_divider);
994 			cpu_to_le16((uint16_t)bp_params->feedback_divider);
996 			(uint8_t)bp_params->fractional_feedback_divider;
998 			(uint8_t)bp_params->pixel_clock_post_divider;
1002 			cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
1008 							bp_params->encoder_object_id));
1011 					bp_params->signal_type, false));
1013 	if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
1016 	if (bp_params->flags.USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK)
1019 	if (CONTROLLER_ID_D1 != bp_params->controller_id)
1048 	struct bp_pixel_clock_parameters *bp_params)
1057 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
1059 					bp_params->controller_id, &controller_id)) {
1063 				(uint8_t)(bp_params->reference_divider);
1065 				cpu_to_le16((uint16_t)(bp_params->feedback_divider));
1067 				cpu_to_le32(bp_params->fractional_feedback_divider);
1069 				(uint8_t)(bp_params->pixel_clock_post_divider);
1073 								bp_params->encoder_object_id));
1076 						bp_params->signal_type, false);
1080 				cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
1082 		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
1086 		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
1095 		if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
1096 			switch (bp_params->color_depth) {
1118 	struct bp_pixel_clock_parameters *bp_params)
1127 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
1129 					bp_params->controller_id, &controller_id)) {
1152 				(uint8_t) bp_params->reference_divider;
1154 				cpu_to_le16((uint16_t) bp_params->feedback_divider);
1156 				cpu_to_le32(bp_params->fractional_feedback_divider);
1158 				(uint8_t) bp_params->pixel_clock_post_divider;
1162 								bp_params->encoder_object_id));
1165 						bp_params->signal_type, false);
1169 				cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
1171 		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
1176 		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC) {
1186 		if (bp_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
1187 			switch (bp_params->color_depth) {
1210 	struct bp_pixel_clock_parameters *bp_params)
1219 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
1220 			&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
1242 		clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
1243 		clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
1245 		clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock_100hz);
1247 		clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
1249 		if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
1252 		if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
1255 		if (bp_params->flags.PROGRAM_PHY_PLL_ONLY)
1258 		if (bp_params->flags.SUPPORT_YUV_420)
1261 		if (bp_params->flags.SET_XTALIN_REF_SRC)
1264 		if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC)
1267 		if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
1285 	struct bp_spread_spectrum_parameters *bp_params,
1289 	struct bp_spread_spectrum_parameters *bp_params,
1293 	struct bp_spread_spectrum_parameters *bp_params,
1321 	struct bp_spread_spectrum_parameters *bp_params,
1329 	if ((enable == true) && (bp_params->percentage > 0))
1335 			cpu_to_le16((uint16_t)bp_params->percentage);
1337 			(uint8_t)bp_params->ver1.step;
1339 			(uint8_t)bp_params->ver1.delay;
1342 			(uint8_t)(bp_params->ver1.range / 10000);
1344 	if (bp_params->flags.EXTERNAL_SS)
1347 	if (bp_params->flags.CENTER_SPREAD)
1350 	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
1352 	else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
1365 	struct bp_spread_spectrum_parameters *bp_params,
1373 	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
1375 	else if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL2)
1380 	if ((enable == true) && (bp_params->percentage > 0)) {
1384 				cpu_to_le16((uint16_t)(bp_params->percentage));
1386 				cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
1388 		if (bp_params->flags.EXTERNAL_SS)
1392 		if (bp_params->flags.CENTER_SPREAD)
1400 				((bp_params->ds.feedback_amount <<
1403 						((bp_params->ds.nfrac_amount <<
1417 	struct bp_spread_spectrum_parameters *bp_params,
1425 	switch (bp_params->pll_id) {
1454 				cpu_to_le16((uint16_t)(bp_params->ds_frac_amount));
1456 				cpu_to_le16((uint16_t)(bp_params->ds.ds_frac_size));
1458 		if (bp_params->flags.EXTERNAL_SS)
1461 		if (bp_params->flags.CENTER_SPREAD)
1469 				((bp_params->ds.feedback_amount <<
1472 						((bp_params->ds.nfrac_amount <<
1494 	struct bp_adjust_pixel_clock_parameters *bp_params);
1497 	struct bp_adjust_pixel_clock_parameters *bp_params);
1518 	struct bp_adjust_pixel_clock_parameters *bp_params)
1525 	uint32_t pixel_clock_10KHz_in = bp_params->pixel_clock / 10;
1531 							bp_params->encoder_object_id));
1534 					bp_params->signal_type, false);
1542 		uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
1545 			bp_params->adjusted_pixel_clock =
1549 			bp_params->adjusted_pixel_clock = 0;
1561 	struct bp_adjust_pixel_clock_parameters *bp_params)
1565 	uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
1575 							bp_params->encoder_object_id));
1578 					bp_params->signal_type, false);
1580 	if (bp_params->ss_enable == true)
1583 	if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK)
1592 		uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock;
1595 			bp_params->adjusted_pixel_clock =
1599 			bp_params->adjusted_pixel_clock = 0;
1603 		bp_params->reference_divider = params.sOutput.ucRefDiv;
1604 		bp_params->pixel_clock_post_divider = params.sOutput.ucPostDiv;
1789 	struct bp_hw_crtc_timing_parameters *bp_params);
1792 	struct bp_hw_crtc_timing_parameters *bp_params);
1825 	struct bp_hw_crtc_timing_parameters *bp_params)
1832 			bp_params->controller_id, &atom_controller_id))
1835 	params.usH_Total = cpu_to_le16((uint16_t)(bp_params->h_total));
1836 	params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable));
1837 	params.usH_SyncStart = cpu_to_le16((uint16_t)(bp_params->h_sync_start));
1838 	params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width));
1839 	params.usV_Total = cpu_to_le16((uint16_t)(bp_params->v_total));
1840 	params.usV_Disp = cpu_to_le16((uint16_t)(bp_params->v_addressable));
1842 			cpu_to_le16((uint16_t)(bp_params->v_sync_start));
1844 			cpu_to_le16((uint16_t)(bp_params->v_sync_width));
1852 	params.ucOverscanRight = (uint8_t)bp_params->h_overscan_right;
1853 	params.ucOverscanLeft = (uint8_t)bp_params->h_overscan_left;
1854 	params.ucOverscanBottom = (uint8_t)bp_params->v_overscan_bottom;
1855 	params.ucOverscanTop = (uint8_t)bp_params->v_overscan_top;
1857 	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
1861 	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
1865 	if (bp_params->flags.INTERLACE) {
1883 				cpu_to_le16((uint16_t)(bp_params->v_sync_start + 1));
1886 	if (bp_params->flags.HORZ_COUNT_BY_TWO)
1898 	struct bp_hw_crtc_timing_parameters *bp_params)
1905 			bp_params->controller_id, &atom_controller_id))
1909 	params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable);
1912 			cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable));
1914 	params.usV_Size = cpu_to_le16((uint16_t)bp_params->v_addressable);
1917 			cpu_to_le16((uint16_t)(bp_params->v_total - bp_params->v_addressable));
1922 			cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable));
1923 	params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width);
1928 			cpu_to_le16((uint16_t)(bp_params->v_sync_start - bp_params->v_addressable));
1929 	params.usV_SyncWidth = cpu_to_le16((uint16_t)bp_params->v_sync_width);
1936 	if (0 == bp_params->flags.HSYNC_POSITIVE_POLARITY)
1940 	if (0 == bp_params->flags.VSYNC_POSITIVE_POLARITY)
1944 	if (bp_params->flags.INTERLACE)	{
1967 	if (bp_params->flags.HORZ_COUNT_BY_TWO)
2090 	struct bp_pixel_clock_parameters *bp_params);
2093 	struct bp_pixel_clock_parameters *bp_params);
2114 	struct bp_pixel_clock_parameters *bp_params)
2123 			bp_params->pll_id, &atom_pll_id)) {
2131 			cpu_to_le16((uint16_t) (bp_params->target_pixel_clock_100hz / 100));
2134 	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
2145 	struct bp_pixel_clock_parameters *bp_params)
2155 			bp_params->pll_id, &atom_pll_id)) {
2163 			cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
2165 	if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
2168 	if (bp_params->flags.SET_DISPCLK_DFS_BYPASS)
2174 		bp_params->dfs_bypass_display_clock =
2371 	struct bp_set_dce_clock_parameters *bp_params);
2389 	struct bp_set_dce_clock_parameters *bp_params)
2400 	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
2401 			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
2407 	if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
2408 		if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
2411 		if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK)
2414 		if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK)
2417 		if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK)
2423 		params.asParam.ulDCEClkFreq = cpu_to_le32(bp_params->target_clock_frequency / 10);
2427 		bp_params->target_clock_frequency = le32_to_cpu(params.asParam.ulDCEClkFreq) * 10;