display/amdgpu_dm/amdgpu_dm_plane.c

95 	return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]);
167 static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)
169 	return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
172 static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier)
174 	if (modifier == DRM_FORMAT_MOD_LINEAR)
177 	return AMD_FMT_MOD_GET(TILE, modifier);
235 								uint64_t modifier)
237 	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
238 	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
239 	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
246 	if (!IS_AMD_FMT_MOD(modifier))
316 	const uint64_t modifier = afb->base.modifier;
319 	amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
320 	tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);
322 	if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) {
324 		bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
325 		bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
330 		if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
1392 						 uint64_t modifier)
1398 	enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3;
1408 	if (modifier == DRM_FORMAT_MOD_LINEAR ||
1409 	    modifier == DRM_FORMAT_MOD_INVALID) {
1413 	/* Check that the modifier is on the list of the plane's supported modifiers. */
1415 		if (modifier == plane->modifiers[i])
1422 	 * For D swizzle the canonical modifier depends on the bpp, so check
1425 	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 &&
1435 	if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {