Lines Matching refs:stream
265 if (!acrtc->dm_irq_params.stream) {
271 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
286 if (!acrtc->dm_irq_params.stream) {
299 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
378 * DC has a generic way to update planes and stream via
387 * @stream: stream state
388 * @stream_update: stream update
395 struct dc_stream_state *stream,
410 stream,
462 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
559 if (acrtc->dm_irq_params.stream &&
564 acrtc->dm_irq_params.stream,
569 acrtc->dm_irq_params.stream,
607 struct dc_stream_state *stream = acrtc->dm_irq_params.stream;
609 v_total = stream->adjust.v_total_max ?
610 stream->adjust.v_total_max : stream->timing.v_total;
611 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz *
612 100LL, (v_total * stream->timing.h_total));
617 acrtc->dm_irq_params.stream, 0);
651 if (acrtc->dm_irq_params.stream &&
656 acrtc->dm_irq_params.stream,
659 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
2653 struct dc_stream_state *stream = context->streams[i];
2655 del_streams[del_streams_count++] = stream;
2854 bundle->stream_update.stream = dc_state->streams[k];
3044 if (dm_new_crtc_state->stream) {
3045 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
3046 dc_stream_release(dm_new_crtc_state->stream);
3047 dm_new_crtc_state->stream = NULL;
3221 * For S3 resume with headless use eml_sink to fake stream
5412 struct dc_stream_state *stream)
5417 struct rect dst = { 0 }; /* stream addressable area */
5426 dst.width = stream->timing.h_addressable;
5427 dst.height = stream->timing.v_addressable;
5446 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5447 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5457 stream->src = src;
5458 stream->dst = dst;
5647 struct dc_stream_state *stream,
5654 struct dc_crtc_timing *timing_out = &stream->timing;
5672 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5679 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5704 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5735 stream->out_transfer_func.type = TF_TYPE_PREDEFINED;
5736 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB;
5737 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5746 stream->output_color_space = get_output_color_space(timing_out, connector_state);
5747 stream->content_type = get_output_content_type(connector_state);
5851 struct dc_stream_state *stream)
5855 if (stream->triggered_crtc_reset.enabled) {
5856 master = stream->triggered_crtc_reset.event_source;
5857 stream->triggered_crtc_reset.event =
5860 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5890 struct dc_stream_state *stream;
5907 stream = context->streams[i];
5909 if (!stream)
5912 set_multisync_trigger_params(stream);
6030 struct dc_sink *sink, struct dc_stream_state *stream,
6033 stream->timing.flags.DSC = 0;
6049 struct dc_sink *sink, struct dc_stream_state *stream,
6064 verified_link_cap = dc_link_get_link_cap(stream->link);
6065 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
6079 &stream->timing,
6088 &stream->timing,
6091 stream->timing.dsc_cfg = dsc_cfg;
6092 stream->timing.flags.DSC = 1;
6093 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
6103 &stream->timing,
6106 stream->timing.dsc_cfg = dsc_cfg;
6107 stream->timing.flags.DSC = 1;
6113 struct dc_sink *sink, struct dc_stream_state *stream,
6139 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
6147 &stream->timing,
6149 &stream->timing.dsc_cfg)) {
6150 stream->timing.flags.DSC = 1;
6154 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6166 &stream->timing,
6168 &stream->timing.dsc_cfg)) {
6169 stream->timing.flags.DSC = 1;
6176 /* Overwrite the stream flag if DSC is enabled through debugfs */
6178 stream->timing.flags.DSC = 1;
6180 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6181 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6183 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6184 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6186 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6187 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6200 struct dc_stream_state *stream = NULL;
6220 return stream;
6239 return stream;
6246 stream = dc_create_stream_for_sink(sink);
6248 if (stream == NULL) {
6249 DRM_ERROR("Failed to create stream for sink!\n");
6254 stream->dm_stream_context = aconnector;
6256 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6308 stream, &mode, connector, con_state, NULL,
6312 stream, &mode, connector, con_state, old_stream,
6322 stream->timing.display_color_depth,
6324 stream->timing = *aconnector->timing_requested;
6328 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6330 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6332 update_stream_scaling_settings(&mode, dm_state, stream);
6335 &stream->audio_info,
6339 update_stream_signal(stream, sink);
6341 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6342 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6344 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
6345 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
6346 stream->signal == SIGNAL_TYPE_EDP) {
6348 // should decide stream support vsc sdp colorimetry capability
6351 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
6352 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED;
6354 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
6356 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6363 return stream;
6812 struct dc_stream_state *stream)
6818 if (!stream)
6829 /* populate stream to plane */
6830 dc_plane_state->src_rect.height = stream->src.height;
6831 dc_plane_state->src_rect.width = stream->src.width;
6832 dc_plane_state->dst_rect.height = stream->src.height;
6833 dc_plane_state->dst_rect.width = stream->src.width;
6834 dc_plane_state->clip_rect.height = stream->src.height;
6835 dc_plane_state->clip_rect.width = stream->src.width;
6836 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6837 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6838 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6839 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6840 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6847 dc_result = dc_validate_stream(dc, stream);
6852 dc_result = dc_state_add_stream(dc, dc_state, stream);
6856 stream,
6882 struct dc_stream_state *stream;
6888 stream = create_stream_for_sink(connector, drm_mode,
6891 if (stream == NULL) {
6892 DRM_ERROR("Failed to create stream for sink!\n");
6897 return stream;
6899 dc_result = dc_validate_stream(adev->dm.dc, stream);
6900 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6901 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6904 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6914 dc_stream_release(stream);
6915 stream = NULL;
6919 } while (stream == NULL && requested_bpc >= 6);
6925 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6930 return stream;
6938 /* TODO: Unhardcode stream count */
6939 struct dc_stream_state *stream;
6964 stream = create_validate_stream_for_sink(aconnector, mode,
6967 if (stream) {
6968 dc_stream_release(stream);
7088 * DC considers the stream backends changed if the
7208 struct dc_stream_state *stream = NULL;
7232 stream = dc_state->streams[j];
7233 if (!stream)
7236 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
7239 stream = NULL;
7242 if (!stream)
7245 pbn_div = dm_mst_get_pbn_divider(stream->link);
7259 if (stream->timing.flags.DSC != 1) {
8116 struct dc_stream_state *stream)
8188 new_crtc_state->stream,
8242 struct dc_stream_state *new_stream = new_crtc_state->stream;
8334 * TODO: Make this per-stream so we don't issue redundant updates for
8405 /* Cursor plane is handled after stream updates */
8465 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8466 acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8470 acrtc_state->stream->link->psr_settings.psr_version ==
8480 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8487 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8489 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8490 amdgpu_dm_psr_disable(acrtc_state->stream);
8530 acrtc_state->stream,
8603 if (acrtc_state->stream) {
8606 &acrtc_state->stream->vrr_infopacket;
8622 acrtc_state->stream) {
8630 bundle->stream_update.stream = acrtc_state->stream;
8632 bundle->stream_update.src = acrtc_state->stream->src;
8633 bundle->stream_update.dst = acrtc_state->stream->dst;
8639 * already modified the stream in place.
8642 &acrtc_state->stream->gamut_remap_matrix;
8644 &acrtc_state->stream->csc_color_matrix;
8646 &acrtc_state->stream->out_transfer_func;
8648 (struct dc_3dlut *) acrtc_state->stream->lut3d_func;
8650 (struct dc_transfer_func *) acrtc_state->stream->func_shaper;
8653 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8659 acrtc_state->stream->link->psr_settings.psr_allow_active)
8660 amdgpu_dm_psr_disable(acrtc_state->stream);
8664 * If FreeSync state on the stream has changed then we need to
8671 dm->dc, acrtc_state->stream,
8679 acrtc_state->stream,
8701 if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
8702 !acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8704 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8705 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
8706 } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8707 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8710 acrtc_state->stream->dm_stream_context;
8713 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8719 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8721 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8736 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8741 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8744 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8746 amdgpu_dm_psr_enable(acrtc_state->stream);
8826 if (!new_dm_crtc_state->stream)
8829 status = dc_stream_get_status(new_dm_crtc_state->stream);
8850 * @stream_state: the DC stream state.
8864 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
8919 dc_stream_release(dm_old_crtc_state->stream);
8948 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8953 if (dm_new_crtc_state->stream) {
8955 dm_new_crtc_state->stream);
8962 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8966 if (!dm_new_crtc_state->stream) {
8982 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8987 if (dm_old_crtc_state->stream)
8988 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8999 if (dm_old_crtc_state->stream)
9000 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
9029 if (dm_new_crtc_state->stream != NULL) {
9031 dc_stream_get_status(dm_new_crtc_state->stream);
9035 dm_new_crtc_state->stream);
9038 "got no status for stream %p on acrtc%p\n",
9039 dm_new_crtc_state->stream, acrtc);
9080 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) {
9138 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info);
9258 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
9343 stream_update.stream = dm_new_crtc_state->stream;
9346 dm_new_con_state, dm_new_crtc_state->stream);
9348 stream_update.src = dm_new_crtc_state->stream->src;
9349 stream_update.dst = dm_new_crtc_state->stream->dst;
9353 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
9363 status = dc_stream_get_status(dm_new_crtc_state->stream);
9371 * TODO: DC refuses to perform stream updates without a dc_surface_update.
9373 * To fix this, DC should permit updating only stream properties.
9388 dm_new_crtc_state->stream,
9424 dc_stream_retain(dm_new_crtc_state->stream);
9425 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
9437 * settings for the stream.
9469 if (dm_new_crtc_state->stream)
9632 if (!acrtc_state->stream)
9640 if (acrtc_state->stream->sink != aconnector->dc_sink)
9715 new_crtc_state->stream->ignore_msa_timing_param = true;
9845 dm_old_crtc_state->stream);
9848 * we can have no stream on ACTION_SET if a display
9855 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9876 * If we already removed the old stream from the context
9877 * (and set the new stream to NULL) then we can't reuse
9878 * the old stream even if the stream and scaling are unchanged.
9885 dm_new_crtc_state->stream &&
9889 if (dm_new_crtc_state->stream &&
9890 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9891 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9912 /* Remove stream for any changed/disabled CRTC */
9915 if (!dm_old_crtc_state->stream)
9925 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9926 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9927 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9959 dm_old_crtc_state->stream) != DC_OK) {
9964 dc_stream_release(dm_old_crtc_state->stream);
9965 dm_new_crtc_state->stream = NULL;
9971 } else {/* Add stream for any updated/enabled CRTC */
9984 dm_old_crtc_state->stream)) {
9986 WARN_ON(dm_new_crtc_state->stream);
9992 dm_new_crtc_state->stream = new_stream;
10002 dm_new_crtc_state->stream) != DC_OK) {
10017 * We want to do dc stream updates that do not require a
10028 * => The dc stream state currently exists.
10030 BUG_ON(dm_new_crtc_state->stream == NULL);
10036 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
10311 if (!dm_old_crtc_state->stream)
10323 dm_old_crtc_state->stream,
10349 if (!dm_new_crtc_state->stream)
10395 * to the stream, and therefore part of the atomic
10401 dm_new_crtc_state->stream,
10596 * might not seem necessary. This is because DC stream creation requires the
10855 * new stream into context w\o causing full reset. Need to