display/amdgpu_dm/amdgpu_dm.c

427 	unsigned long flags;
441 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
448 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
511 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
526 	unsigned long flags;
561 				spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
571 				spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
590 	unsigned long flags;
599 			spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags);
603 			spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags);
649 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
684 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
1388 	unsigned long flags;
1418 		spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1420 		spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1460 		spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1462 		spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1665 			init_data.flags.disable_dmcu = false;
1668 			init_data.flags.disable_dmcu = true;
1672 		init_data.flags.disable_dmcu = true;
1684 		init_data.flags.gpu_vm_support = false;
1687 			init_data.flags.gpu_vm_support = false;
1689 			init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1691 		init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1694 	adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1697 		init_data.flags.fbc_support = true;
1700 		init_data.flags.multi_mon_pp_mclk_switch = true;
1703 		init_data.flags.disable_fractional_pwm = true;
1706 		init_data.flags.edp_no_power_sequencing = true;
1709 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1711 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1713 	init_data.flags.seamless_boot_edp_requested = false;
1716 		init_data.flags.seamless_boot_edp_requested = true;
1717 		init_data.flags.allow_seamless_boot_optimization = true;
1721 	init_data.flags.enable_mipi_converter_optimization = true;
1728 		init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
1730 	init_data.flags.disable_ips_in_vpb = 1;
1798 	if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
5523 		if (dc_crtc_timing->flags.Y_ONLY)
5529 		if (dc_crtc_timing->flags.Y_ONLY)
5554 			if (dc_crtc_timing->flags.Y_ONLY)
5560 			if (dc_crtc_timing->flags.Y_ONLY)
5675 		timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5676 		timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5679 		if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5680 			timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5681 		if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5682 			timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5764 	audio_info->flags.all = edid_caps->speaker_flags;
5839 			master->timing.flags.VSYNC_POSITIVE_POLARITY ?
6014 	stream->timing.flags.DSC = 0;
6073 				stream->timing.flags.DSC = 1;
6088 		stream->timing.flags.DSC = 1;
6131 				stream->timing.flags.DSC = 1;
6150 					stream->timing.flags.DSC = 1;
6159 		stream->timing.flags.DSC = 1;
6161 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6164 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6167 	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6237 	stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6923 	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6924 			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
7240 		if (stream->timing.flags.DSC != 1) {
7737 		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
8135 	unsigned long flags;
8151 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8216 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8228 	unsigned long flags;
8240 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8275 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8347 	unsigned long flags;
8542 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8544 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8576 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8581 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8593 		spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8598 		spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8650 			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8654 			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8829  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8833  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8834  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8932 		/* Copy all transient state flags into dc state */
9143 	unsigned long flags;
9396 		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9398 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9422 					spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9430 					spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9492 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9500 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
10210 	 * check tiling flags when the FB doesn't have a modifier.
10212 	if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
11322 				if (range->flags != 1)