amd/amdkfd/kfd_svm.c

217 		struct kfd_process_device *pdd;
220 		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
221 		if (!pdd) {
226 		r = svm_range_dma_map_dev(pdd->dev->adev, prange, offset, npages,
255 	struct kfd_process_device *pdd;
268 		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
269 		if (!pdd) {
273 		dev = &pdd->dev->adev->pdev->dev;
654 	struct kfd_process_device *pdd;
657 	pdd = kfd_process_device_data_by_id(p, gpu_id);
658 	if (!pdd) {
663 	return pdd->dev;
1290 	struct kfd_process_device *pdd;
1313 		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
1314 		if (!pdd) {
1319 		kfd_smi_event_unmap_from_gpu(pdd->dev, p->lead_thread->pid,
1322 		r = svm_range_unmap_from_gpu(pdd->dev->adev,
1323 					     drm_priv_to_vm(pdd->drm_priv),
1335 		kfd_flush_tlb(pdd, TLB_FLUSH_HEAVYWEIGHT);
1342 svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange,
1347 	struct amdgpu_device *adev = pdd->dev->adev;
1348 	struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
1374 		pte_flags = svm_range_get_pte_flags(pdd->dev, prange, last_domain);
1423 	struct kfd_process_device *pdd;
1436 		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
1437 		if (!pdd) {
1442 		pdd = kfd_bind_process_to_device(pdd->dev, p);
1443 		if (IS_ERR(pdd))
1446 		if (bo_adev && pdd->dev->adev != bo_adev &&
1447 		    !amdgpu_xgmi_same_hive(pdd->dev->adev, bo_adev)) {
1452 		r = svm_range_map_to_gpu(pdd, prange, offset, npages, readonly,
1469 		kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
1485 	struct kfd_process_device *pdd;
1493 			pdd = kfd_process_device_from_gpuidx(ctx->process, gpuidx);
1494 			if (!pdd) {
1499 			vm = drm_priv_to_vm(pdd->drm_priv);
1511 		pdd = kfd_process_device_from_gpuidx(ctx->process, gpuidx);
1512 		if (!pdd) {
1518 		r = amdgpu_vm_validate(pdd->dev->adev,
1519 				       drm_priv_to_vm(pdd->drm_priv), NULL,
1541 	struct kfd_process_device *pdd;
1543 	pdd = kfd_process_device_from_gpuidx(p, gpuidx);
1544 	if (!pdd)
1547 	return SVM_ADEV_PGMAP_OWNER(pdd->dev->adev);
2249 	struct kfd_process_device *pdd;
2262 		pdd = p->pdds[i];
2263 		if (!pdd)
2268 		amdgpu_ih_wait_on_checkpoint_process_ts(pdd->dev->adev,
2269 				pdd->dev->adev->irq.retry_cam_enabled ?
2270 				&pdd->dev->adev->irq.ih :
2271 				&pdd->dev->adev->irq.ih1);
2273 		if (pdd->dev->adev->irq.retry_cam_enabled)
2274 			amdgpu_ih_wait_on_checkpoint_process_ts(pdd->dev->adev,
2275 				&pdd->dev->adev->irq.ih_soft);
2849 	struct kfd_process_device *pdd;
2867 	pdd = kfd_process_device_from_gpuidx(p, gpuidx);
2868 	if (pdd)
2869 		WRITE_ONCE(pdd->faults, pdd->faults + 1);
3209  * It looks for each pdd in the kfd_process.
3323 	struct kfd_process_device *pdd;
3352 		pdd = kfd_process_device_from_gpuidx(p, gpuidx);
3353 		if (!pdd) {
3358 		if (pdd->dev->adev == bo_node->adev)
3361 		if (!svm_nodes_in_same_hive(pdd->dev, bo_node)) {
4075 		struct kfd_process_device *pdd = p->pdds[index];
4079 		query_attr[index + nattr_common].value = pdd->user_gpu_id;