amd/amdkfd/kfd_packet_manager_vi.c

45 	struct pm4_mes_map_process *packet;
47 	packet = (struct pm4_mes_map_process *)buffer;
51 	packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
53 	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
54 	packet->bitfields2.process_quantum = 10;
55 	packet->bitfields2.pasid = qpd->pqm->process->pasid;
56 	packet->bitfields3.page_table_base = qpd->page_table_base;
57 	packet->bitfields10.gds_size = qpd->gds_size;
58 	packet->bitfields10.num_gws = qpd->num_gws;
59 	packet->bitfields10.num_oac = qpd->num_oac;
60 	packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
62 	packet->sh_mem_config = qpd->sh_mem_config;
63 	packet->sh_mem_bases = qpd->sh_mem_bases;
64 	packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base;
65 	packet->sh_mem_ape1_limit = qpd->sh_mem_ape1_limit;
67 	packet->sh_hidden_private_base_vmid = qpd->sh_hidden_private_base;
69 	packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
70 	packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
78 	struct pm4_mes_runlist *packet;
97 	packet = (struct pm4_mes_runlist *)buffer;
100 	packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
103 	packet->bitfields4.ib_size = ib_size_in_dwords;
104 	packet->bitfields4.chain = chain ? 1 : 0;
105 	packet->bitfields4.offload_polling = 0;
106 	packet->bitfields4.valid = 1;
107 	packet->bitfields4.process_cnt = concurrent_proc_cnt;
108 	packet->ordinal2 = lower_32_bits(ib);
109 	packet->bitfields3.ib_base_hi = upper_32_bits(ib);
117 	struct pm4_mes_set_resources *packet;
119 	packet = (struct pm4_mes_set_resources *)buffer;
122 	packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
125 	packet->bitfields2.queue_type =
127 	packet->bitfields2.vmid_mask = res->vmid_mask;
128 	packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
129 	packet->bitfields7.oac_mask = res->oac_mask;
130 	packet->bitfields8.gds_heap_base = res->gds_heap_base;
131 	packet->bitfields8.gds_heap_size = res->gds_heap_size;
133 	packet->gws_mask_lo = lower_32_bits(res->gws_mask);
134 	packet->gws_mask_hi = upper_32_bits(res->gws_mask);
136 	packet->queue_mask_lo = lower_32_bits(res->queue_mask);
137 	packet->queue_mask_hi = upper_32_bits(res->queue_mask);
145 	struct pm4_mes_map_queues *packet;
148 	packet = (struct pm4_mes_map_queues *)buffer;
151 	packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
153 	packet->bitfields2.num_queues = 1;
154 	packet->bitfields2.queue_sel =
157 	packet->bitfields2.engine_sel =
159 	packet->bitfields2.queue_type =
165 			packet->bitfields2.queue_type =
169 		packet->bitfields2.queue_type =
174 		packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
182 	packet->bitfields3.doorbell_offset =
185 	packet->mqd_addr_lo =
188 	packet->mqd_addr_hi =
191 	packet->wptr_addr_lo =
194 	packet->wptr_addr_hi =
204 	struct pm4_mes_unmap_queues *packet;
206 	packet = (struct pm4_mes_unmap_queues *)buffer;
209 	packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
212 	packet->bitfields2.engine_sel =
216 		packet->bitfields2.action =
219 		packet->bitfields2.action =
224 		packet->bitfields2.queue_sel =
226 		packet->bitfields3a.pasid = filter_param;
229 		packet->bitfields2.queue_sel =
234 		packet->bitfields2.queue_sel =
249 	struct pm4_mes_query_status *packet;
251 	packet = (struct pm4_mes_query_status *)buffer;
254 	packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
257 	packet->bitfields2.context_id = 0;
258 	packet->bitfields2.interrupt_sel =
260 	packet->bitfields2.command =
263 	packet->addr_hi = upper_32_bits((uint64_t)fence_address);
264 	packet->addr_lo = lower_32_bits((uint64_t)fence_address);
265 	packet->data_hi = upper_32_bits((uint64_t)fence_value);
266 	packet->data_lo = lower_32_bits((uint64_t)fence_value);
273 	struct pm4_mec_release_mem *packet;
275 	packet = (struct pm4_mec_release_mem *)buffer;
276 	memset(buffer, 0, sizeof(*packet));
278 	packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
279 						 sizeof(*packet));
281 	packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
282 	packet->bitfields2.event_index = event_index___release_mem__end_of_pipe;
283 	packet->bitfields2.tcl1_action_ena = 1;
284 	packet->bitfields2.tc_action_ena = 1;
285 	packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
286 	packet->bitfields2.atc = 0;
288 	packet->bitfields3.data_sel = data_sel___release_mem__send_32_bit_low;
289 	packet->bitfields3.int_sel =
292 	packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
293 	packet->address_hi = upper_32_bits(gpu_addr);
295 	packet->data_lo = 0;