amd/amdkfd/kfd_flat_memory.c

317 static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id)
323 	pdd->lds_base = MAKE_LDS_APP_BASE_VI();
324 	pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
330 	pdd->gpuvm_base = max(SVM_USER_BASE, AMDGPU_VA_RESERVED_BOTTOM);
331 	pdd->gpuvm_limit =
332 		pdd->dev->kfd->shared_resources.gpuvm_size - 1;
337 	pdd->qpd.cwsr_base = SVM_CWSR_BASE;
338 	pdd->qpd.ib_base = SVM_IB_BASE;
340 	pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI();
341 	pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
344 static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id)
346 	pdd->lds_base = MAKE_LDS_APP_BASE_V9();
347 	pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
349 	pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM;
350 	pdd->gpuvm_limit =
351 		pdd->dev->kfd->shared_resources.gpuvm_size - 1;
353 	pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();
354 	pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
360 	pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev);
367 	struct kfd_process_device *pdd;
381 		pdd = kfd_create_process_device_data(dev, process);
382 		if (!pdd) {
392 			pdd->lds_base = pdd->lds_limit = 0;
393 			pdd->gpuvm_base = pdd->gpuvm_limit = 0;
394 			pdd->scratch_base = pdd->scratch_limit = 0;
406 				kfd_init_apertures_vi(pdd, id);
410 					kfd_init_apertures_v9(pdd, id);
420 		dev_dbg(kfd_device, "gpu id %u\n", pdd->dev->id);
421 		dev_dbg(kfd_device, "lds_base %llX\n", pdd->lds_base);
422 		dev_dbg(kfd_device, "lds_limit %llX\n", pdd->lds_limit);
423 		dev_dbg(kfd_device, "gpuvm_base %llX\n", pdd->gpuvm_base);
424 		dev_dbg(kfd_device, "gpuvm_limit %llX\n", pdd->gpuvm_limit);
425 		dev_dbg(kfd_device, "scratch_base %llX\n", pdd->scratch_base);
426 		dev_dbg(kfd_device, "scratch_limit %llX\n", pdd->scratch_limit);