amd/amdkfd/kfd_device_queue_manager.c

41 /* Size of the per-pipe EOP queue */
78 static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
82 		+ pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;
575 		pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
576 			q->pipe, q->queue);
617 			retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
659 	int pipe, bit, i;
663 	for (pipe = dqm->next_pipe_to_allocate, i = 0;
665 			pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
667 		if (!is_pipe_enabled(dqm, 0, pipe))
670 		if (dqm->allocated_queues[pipe] != 0) {
671 			bit = ffs(dqm->allocated_queues[pipe]) - 1;
672 			dqm->allocated_queues[pipe] &= ~(1 << bit);
673 			q->pipe = pipe;
683 	pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
685 	dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
693 	dqm->allocated_queues[q->pipe] |= (1 << q->queue);
799 				q->pipe, q->queue);
904 				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
951 						   q->pipe, q->queue,
1083 				KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1216 		retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
1404 	int pipe, queue;
1419 	for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1420 		int pipe_offset = pipe * get_queues_per_pipe(dqm);
1425 				dqm->allocated_queues[pipe] |= 1 << queue;
3190 	int pipe, queue;
3217 		for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
3218 			int pipe_offset = pipe * get_queues_per_pipe(dqm);
3226 								pipe, queue,
3234 					   xcc_id, pipe, queue);
3243 	for (pipe = sdma_engine_start;
3244 	     pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));
3245 	     pipe++) {
3250 				dqm->dev->adev, pipe, queue, &dump, &n_regs);
3255 				  pipe, queue);