Lines Matching refs:by
107 var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data
221 // Caused by instruction fetch memory violation.
307 // If not caused by trap then halt wave to prevent re-entry.
334 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32
335 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32
370 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic
752 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW
825 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group
895 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic
911 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32
912 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32
913 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu