Lines Matching defs:var
30 var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23
31 var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000
32 var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1
33 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006
34 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0
35 var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1
36 var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3
37 var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29
39 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12
40 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9
41 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8
42 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6
43 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24
44 var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
46 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400
47 var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask
48 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10
49 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100
50 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8
51 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF
52 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0
53 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10
54 var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800
55 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11
56 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21
58 var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME
59 var SQ_WAVE_IB_STS_RCNT_SIZE = 4 //FIXME
60 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME
61 var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME
62 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME
64 var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24
65 var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27
69 var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes
70 var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
72 var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit
73 var S_SAVE_SPI_INIT_ATC_SHIFT = 27
74 var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype
75 var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28
76 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG
77 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26
79 var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used
80 var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME
81 var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME
82 var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME
84 var s_save_spi_init_lo = exec_lo
85 var s_save_spi_init_hi = exec_hi
88 var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
89 var s_save_pc_hi = ttmp1
90 var s_save_exec_lo = ttmp2
91 var s_save_exec_hi = ttmp3
92 var s_save_status = ttmp4
93 var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine
94 var s_save_xnack_mask_lo = ttmp6
95 var s_save_xnack_mask_hi = ttmp7
96 var s_save_buf_rsrc0 = ttmp8
97 var s_save_buf_rsrc1 = ttmp9
98 var s_save_buf_rsrc2 = ttmp10
99 var s_save_buf_rsrc3 = ttmp11
101 var s_save_mem_offset = tma_lo
102 var s_save_alloc_size = s_save_trapsts //conflict
103 var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time)
104 var s_save_m0 = tma_hi
107 var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE
108 var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC
110 var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit
111 var S_RESTORE_SPI_INIT_ATC_SHIFT = 27
112 var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype
113 var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28
114 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG
115 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26
117 var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT
118 var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK
119 var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
120 var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK
122 var s_restore_spi_init_lo = exec_lo
123 var s_restore_spi_init_hi = exec_hi
125 var s_restore_mem_offset = ttmp2
126 var s_restore_alloc_size = ttmp3
127 var s_restore_tmp = ttmp6 //tba_lo/hi need to be restored
128 var s_restore_mem_offset_save = s_restore_tmp //no conflict
130 var s_restore_m0 = s_restore_alloc_size //no conflict
132 var s_restore_mode = ttmp7
134 var s_restore_pc_lo = ttmp0
135 var s_restore_pc_hi = ttmp1
136 var s_restore_exec_lo = tma_lo //no conflict
137 var s_restore_exec_hi = tma_hi //no conflict
138 var s_restore_status = ttmp4
139 var s_restore_trapsts = ttmp5
140 var s_restore_xnack_mask_lo = xnack_mask_lo
141 var s_restore_xnack_mask_hi = xnack_mask_hi
142 var s_restore_buf_rsrc0 = ttmp8
143 var s_restore_buf_rsrc1 = ttmp9
144 var s_restore_buf_rsrc2 = ttmp10
145 var s_restore_buf_rsrc3 = ttmp11