Lines Matching defs:var
49 var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
51 var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006
52 var SQ_WAVE_STATUS_HALT_MASK = 0x2000
53 var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000
54 var SQ_WAVE_STATUS_TRAP_EN_SHIFT = 6
56 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12
57 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9
58 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8
59 var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24
60 var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4
61 var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11
62 var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1
65 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8
67 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12
70 var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400
71 var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF
72 var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10
73 var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80
74 var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7
75 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100
76 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8
77 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF
78 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0
79 var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10
80 var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800
81 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11
82 var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21
83 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800
84 var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000
86 var SQ_WAVE_TRAPSTS_WAVE_START_MASK = 0x20000
87 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x40000
88 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x100000
90 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000
92 var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12
93 var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19
95 var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15
96 var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT = 25
97 var SQ_WAVE_IB_STS_REPLAY_W64H_MASK = 0x02000000
98 var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000
100 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800
103 var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK
105 var S_TRAPSTS_NON_MASKABLE_EXCP_MASK = SQ_WAVE_TRAPSTS_MEM_VIOL_MASK |\
113 var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31
114 var TTMP11_SAVE_REPLAY_W64H_MASK = 0x80000000
115 var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 24
116 var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0x7F000000
117 var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23
118 var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000
122 var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000
123 var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC
124 var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000
125 var S_SAVE_PC_HI_HT_MASK = 0x01000000
126 var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000
127 var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26
129 var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000
130 var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31
132 var s_sgpr_save_num = 108
134 var s_save_spi_init_lo = exec_lo
135 var s_save_spi_init_hi = exec_hi
136 var s_save_pc_lo = ttmp0
137 var s_save_pc_hi = ttmp1
138 var s_save_exec_lo = ttmp2
139 var s_save_exec_hi = ttmp3
140 var s_save_status = ttmp12
141 var s_save_trapsts = ttmp15
142 var s_save_xnack_mask = s_save_trapsts
143 var s_wave_size = ttmp7
144 var s_save_buf_rsrc0 = ttmp8
145 var s_save_buf_rsrc1 = ttmp9
146 var s_save_buf_rsrc2 = ttmp10
147 var s_save_buf_rsrc3 = ttmp11
148 var s_save_mem_offset = ttmp4
149 var s_save_alloc_size = s_save_trapsts
150 var s_save_tmp = ttmp14
151 var s_save_m0 = ttmp5
152 var s_save_ttmps_lo = s_save_tmp
153 var s_save_ttmps_hi = s_save_trapsts
155 var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE
156 var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC
158 var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000
159 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26
160 var S_WAVE_SIZE = 25
162 var s_restore_spi_init_lo = exec_lo
163 var s_restore_spi_init_hi = exec_hi
164 var s_restore_mem_offset = ttmp12
165 var s_restore_alloc_size = ttmp3
166 var s_restore_tmp = ttmp2
167 var s_restore_mem_offset_save = s_restore_tmp
168 var s_restore_m0 = s_restore_alloc_size
169 var s_restore_mode = ttmp7
170 var s_restore_flat_scratch = s_restore_tmp
171 var s_restore_pc_lo = ttmp0
172 var s_restore_pc_hi = ttmp1
173 var s_restore_exec_lo = ttmp4
174 var s_restore_exec_hi = ttmp5
175 var s_restore_status = ttmp14
176 var s_restore_trapsts = ttmp15
177 var s_restore_xnack_mask = ttmp13
178 var s_restore_buf_rsrc0 = ttmp8
179 var s_restore_buf_rsrc1 = ttmp9
180 var s_restore_buf_rsrc2 = ttmp10
181 var s_restore_buf_rsrc3 = ttmp11
182 var s_restore_size = ttmp6
183 var s_restore_ttmps_lo = s_restore_tmp
184 var s_restore_ttmps_hi = s_restore_alloc_size
1260 for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++
1277 for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++
1323 for var lane = 0; lane < 4; ++lane
1336 for var vgpr = 0; vgpr < n_vgprs; ++vgpr
1342 for var vgpr = 0; vgpr < n_vgprs; ++vgpr