Lines Matching refs:vpe
31 #include "ivsrcid/vpe/irqsrcs_vpe_6_1.h"
32 #include "vpe/vpe_6_1_0_offset.h"
33 #include "vpe/vpe_6_1_0_sh_mask.h"
63 static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)
67 base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];
72 static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)
74 struct amdgpu_device *adev = vpe->ring.adev;
77 for (i = 0; i < vpe->num_instances; i++) {
78 f32_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL));
81 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_F32_CNTL), f32_cntl);
85 static int vpe_v6_1_irq_init(struct amdgpu_vpe *vpe)
87 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
92 &adev->vpe.trap_irq);
99 static void vpe_v6_1_set_collaborate_mode(struct amdgpu_vpe *vpe, bool enable)
101 struct amdgpu_device *adev = vpe->ring.adev;
104 if (!vpe->collaborate_mode)
107 for (i = 0; i < vpe->num_instances; i++) {
108 vpe_colla_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL));
111 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CNTL), vpe_colla_cntl);
113 vpe_colla_cfg = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG));
118 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_COLLABORATE_CFG), vpe_colla_cfg);
122 static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
124 struct amdgpu_device *adev = vpe->ring.adev;
132 for (j = 0; j < vpe->num_instances; j++) {
135 ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1));
137 ret = RREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL));
142 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL_6_1_1), ret);
144 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_CNTL), ret);
148 vpe_v6_1_set_collaborate_mode(vpe, true);
150 if (amdgpu_vpe_configure_dpm(vpe))
160 f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL);
165 adev->vpe.cmdbuf_cpu_addr[0] = f32_offset;
166 adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl;
171 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
180 vpe_v6_1_halt(vpe, true);
182 for (j = 0; j < vpe->num_instances; j++) {
185 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET);
187 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0);
189 data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]);
195 WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++));
200 vpe_v6_1_halt(vpe, false);
205 static int vpe_v6_1_ring_start(struct amdgpu_vpe *vpe)
207 struct amdgpu_ring *ring = &vpe->ring;
214 for (i = 0; i < vpe->num_instances; i++) {
217 rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL));
221 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);
224 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0);
225 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0);
226 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0);
227 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0);
230 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO),
232 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI),
237 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
238 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
243 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1);
244 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
245 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
247 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0);
249 doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET));
251 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
253 doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL));
255 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell);
261 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl);
263 ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL));
265 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl);
275 static int vpe_v_6_1_ring_stop(struct amdgpu_vpe *vpe)
277 struct amdgpu_device *adev = vpe->ring.adev;
281 for (i = 0; i < vpe->num_instances; i++) {
283 queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1));
285 queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ));
290 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ_6_1_1), queue_reset);
294 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset);
303 vpe->ring.sched.ready = false;
313 struct amdgpu_vpe *vpe = &adev->vpe;
317 vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1));
319 vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL));
325 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL_6_1_1), vpe_cntl);
327 WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl);
341 amdgpu_fence_process(&adev->vpe.ring);
350 static int vpe_v6_1_set_regs(struct amdgpu_vpe *vpe)
352 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
354 vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR;
355 vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI;
356 vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR;
357 vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI;
358 vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT;
361 vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2_6_1_1;
363 vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2;
365 vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4;
366 vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3;
367 vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4;
368 vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2;
369 vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3;
370 vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1;
371 vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3;
393 void vpe_v6_1_set_funcs(struct amdgpu_vpe *vpe)
395 vpe->funcs = &vpe_v6_1_funcs;
396 vpe->trap_irq.funcs = &vpe_v6_1_trap_irq_funcs;