amd/amdgpu/vega20_ih.c

49  * vega20_ih_init_register_offset - Initialize register offset for ih rings
53  * Initialize register offset ih rings (VEGA20).
59 	if (adev->irq.ih.ring_size) {
60 		ih_regs = &adev->irq.ih.ih_regs;
99  * @ih: amdgpu_ih_ring pointer
105 					    struct amdgpu_ih_ring *ih,
111 	ih_regs = &ih->ih_regs;
118 	if (ih == &adev->irq.ih)
130 		ih->enabled = true;
135 		ih->enabled = false;
136 		ih->rptr = 0;
152 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
156 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
157 		if (ih[i]->ring_size) {
158 			r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
167 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
169 	int rb_bufsz = order_base_2(ih->ring_size / 4);
172 				   MC_SPACE, ih->use_bus_addr ? 1 : 4);
190 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
194 	if (ih->use_doorbell) {
197 						 ih->doorbell_index);
210  * vega20_ih_enable_ring - enable an ih ring buffer
213  * @ih: amdgpu_ih_ring pointer
215  * Enable an ih ring buffer (VEGA20)
218 				 struct amdgpu_ih_ring *ih)
223 	ih_regs = &ih->ih_regs;
226 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
227 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
230 	tmp = vega20_ih_rb_cntl(ih, tmp);
231 	if (ih == &adev->irq.ih)
233 	if (ih == &adev->irq.ih1)
244 	if (ih == &adev->irq.ih) {
245 		/* set the ih ring 0 writeback address whether it's enabled or not */
246 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
247 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
254 	WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
282 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
298 			if (adev->irq.ih.use_bus_addr) {
311 			if (adev->irq.ih.use_bus_addr) {
319 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
320 		if (ih[i]->ring_size) {
321 			ret = vega20_ih_enable_ring(adev, ih[i]);
328 		adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
329 						    adev->irq.ih.doorbell_index);
334 	adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
378  * @ih: amdgpu_ih_ring pointer
386 			      struct amdgpu_ih_ring *ih)
391 	if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
397 		wptr = le32_to_cpu(*ih->wptr_cpu);
403 	ih_regs = &ih->ih_regs;
416 	tmp = (wptr + 32) & ih->ptr_mask;
419 		 wptr, ih->rptr, tmp);
420 	ih->rptr = tmp;
433 	return (wptr & ih->ptr_mask);
440  * @ih: amdgpu_ih_ring pointer
444 			       struct amdgpu_ih_ring *ih)
450 	ih_regs = &ih->ih_regs;
455 		if ((v < ih->ring_size) && (v != ih->rptr))
456 			WDOORBELL32(ih->doorbell_index, ih->rptr);
466  * @ih: amdgpu_ih_ring pointer
471 			       struct amdgpu_ih_ring *ih)
475 	if (ih == &adev->irq.ih_soft)
478 	if (ih->use_doorbell) {
480 		*ih->rptr_cpu = ih->rptr;
481 		WDOORBELL32(ih->doorbell_index, ih->rptr);
484 			vega20_ih_irq_rearm(adev, ih);
486 		ih_regs = &ih->ih_regs;
487 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
551 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
555 	adev->irq.ih.use_doorbell = true;
556 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
563 	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
571 		adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
574 	/* initialize ih control registers offset */