Lines Matching defs:inst_idx
66 int inst_idx, struct dpg_pause_state *new_state);
103 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
107 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
123 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]);
437 * @inst_idx: instance number index
442 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
446 hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
452 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
453 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
454 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
455 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
456 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
457 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
458 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
459 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
461 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
462 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
464 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
466 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
471 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
472 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
474 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
475 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
478 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
484 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
486 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
487 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
492 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
493 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
495 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
496 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
498 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
501 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
503 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
504 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
505 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
507 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
508 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
512 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
513 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
515 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
516 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
518 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
520 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
524 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
525 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
527 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
528 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
530 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
532 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
776 * @inst_idx: instance number index
782 int inst_idx, uint8_t indirect)
812 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
813 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
816 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
817 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
820 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
821 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
824 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
825 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
887 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
899 WREG32_SOC15_DPG_MODE(inst_idx,
904 WREG32_SOC15_DPG_MODE(inst_idx,
913 * @inst_idx: instance number index
918 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
920 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
925 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
928 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
931 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
934 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
937 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
942 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
943 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
947 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
958 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
959 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
961 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
962 VCN, inst_idx, regUVD_MPC_CNTL),
965 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
966 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
972 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
973 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
979 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
980 VCN, inst_idx, regUVD_MPC_SET_MUX),
985 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
989 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
990 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
994 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
995 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
997 vcn_v4_0_enable_ras(adev, inst_idx, indirect);
1000 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1001 VCN, inst_idx, regUVD_MASTINT_EN),
1006 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0);
1008 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1010 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
1011 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1012 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
1014 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1016 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1018 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1019 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1021 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
1022 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
1023 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1025 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1027 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1030 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
1469 * @inst_idx: instance number index
1473 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1478 vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state);
1480 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1484 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1485 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1487 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1491 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1582 * @inst_idx: instance number index
1587 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1594 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1596 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1597 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1601 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1607 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1610 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1614 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1620 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1622 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;