Lines Matching refs:ring
78 * Set ring and irq function pointers
123 struct amdgpu_ring *ring;
184 ring = &adev->vcn.inst[j].ring_dec;
185 ring->use_doorbell = true;
187 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
191 ring->vm_hub = AMDGPU_MMHUB1(0);
193 ring->vm_hub = AMDGPU_MMHUB0(0);
195 sprintf(ring->name, "vcn_dec_%d", j);
196 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
204 ring = &adev->vcn.inst[j].ring_enc[i];
205 ring->use_doorbell = true;
207 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
212 ring->vm_hub = AMDGPU_MMHUB1(0);
214 ring->vm_hub = AMDGPU_MMHUB0(0);
216 sprintf(ring->name, "vcn_enc_%d.%d", j, i);
217 r = amdgpu_ring_init(adev, ring, 512,
293 struct amdgpu_ring *ring;
310 ring = &adev->vcn.inst[j].ring_dec;
312 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
313 ring->doorbell_index, j);
315 r = amdgpu_ring_test_helper(ring);
320 ring = &adev->vcn.inst[j].ring_enc[i];
321 r = amdgpu_ring_test_helper(ring);
341 * Stop the VCN block, mark ring as not ready any more
825 struct amdgpu_ring *ring;
920 ring = &adev->vcn.inst[inst_idx].ring_dec;
922 rb_bufsz = order_base_2(ring->ring_size);
941 (upper_32_bits(ring->gpu_addr) >> 2));
943 /* program the RB_BASE for ring buffer */
945 lower_32_bits(ring->gpu_addr));
947 upper_32_bits(ring->gpu_addr));
949 /* Initialize the ring buffer's read and write pointers */
954 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
956 lower_32_bits(ring->wptr));
968 struct amdgpu_ring *ring;
1112 ring = &adev->vcn.inst[i].ring_dec;
1114 rb_bufsz = order_base_2(ring->ring_size);
1123 /* program the RB_BASE for ring buffer */
1125 lower_32_bits(ring->gpu_addr));
1127 upper_32_bits(ring->gpu_addr));
1129 /* Initialize the ring buffer's read and write pointers */
1132 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1134 lower_32_bits(ring->wptr));
1138 ring = &adev->vcn.inst[i].ring_enc[0];
1139 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1140 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1141 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1142 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1143 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1147 ring = &adev->vcn.inst[i].ring_enc[1];
1148 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1149 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1150 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1151 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1152 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1217 struct amdgpu_ring *ring;
1308 ring = &adev->vcn.inst[i].ring_enc[0];
1309 ring->wptr = 0;
1313 lower_32_bits(ring->gpu_addr));
1316 upper_32_bits(ring->gpu_addr));
1319 ring->ring_size / 4);
1321 ring = &adev->vcn.inst[i].ring_dec;
1322 ring->wptr = 0;
1326 lower_32_bits(ring->gpu_addr));
1330 upper_32_bits(ring->gpu_addr));
1333 rb_bufsz = order_base_2(ring->ring_size);
1454 struct amdgpu_ring *ring;
1488 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1489 ring->wptr = 0;
1490 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1491 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1492 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1493 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1494 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1498 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1499 ring->wptr = 0;
1500 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1501 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1502 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1503 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1504 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1529 * @ring: amdgpu_ring pointer
1533 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1535 struct amdgpu_device *adev = ring->adev;
1537 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1543 * @ring: amdgpu_ring pointer
1547 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1549 struct amdgpu_device *adev = ring->adev;
1551 if (ring->use_doorbell)
1552 return *ring->wptr_cpu_addr;
1554 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1560 * @ring: amdgpu_ring pointer
1564 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1566 struct amdgpu_device *adev = ring->adev;
1568 if (ring->use_doorbell) {
1569 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1570 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1572 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1609 * @ring: amdgpu_ring pointer
1613 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1615 struct amdgpu_device *adev = ring->adev;
1617 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1618 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1620 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1626 * @ring: amdgpu_ring pointer
1630 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1632 struct amdgpu_device *adev = ring->adev;
1634 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1635 if (ring->use_doorbell)
1636 return *ring->wptr_cpu_addr;
1638 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
1640 if (ring->use_doorbell)
1641 return *ring->wptr_cpu_addr;
1643 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
1650 * @ring: amdgpu_ring pointer
1654 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1656 struct amdgpu_device *adev = ring->adev;
1658 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1659 if (ring->use_doorbell) {
1660 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1661 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1663 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1666 if (ring->use_doorbell) {
1667 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1668 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1670 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));